Search results for "Gate array"
showing 10 items of 185 documents
Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec
2013
Smart cameras are used in a large range of applications. Usually the smart cameras transmit the video or/and extracted information from the video scene, frequently on compressed format to fit with the application requirements. An efficient hardware accelerator that can be adapted and provide the required coding performances according to the events detected in the video, the available network bandwidth or user requirements, is therefore a key element for smart camera solutions. We propose in this paper to focus on a key part of the compression system: motion estimation. We have developed a flexible hardware implementation of the motion estimator based on FPGA component, fully compatible with…
Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances
2012
International audience; Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution, etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. In order to reach this goal, we propose in this paper a hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search and variable block siz…
Multiple modular very long instruction word processors based on field programmable gate arrays
2007
Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…
LABCENTER. A remote laboratory system platform
2011
Abstract A web system server especially suited for remote laboratories has been developed. Typical e-learning systems do not offer the possibility to perform a remote laboratory where real experiments can be done online, accessing real hardware located at the University facilities. Allowing students to connect to hardware systems remotely provides them with additional knowledge about real devices; very often, real laboratory devices are time or space restricted. The proposed LABCENTER platform is a general frame designed for remote laboratories connection. The platform is designed to allow an authorized student to connect to hardware systems. As direct hardware systems allow only a single u…
Wireless versus Wired Network-on-Chip to Enable the Multi- Tenant Multi-FPGAs in Cloud
2021
The new era of computing is not CPU-centric but enriched with all the heterogeneous computing resources including the reconfigurable fabric. In multi-FPGA architecture, either deployed within a data center or as a standalone model, inter-FPGA communication is crucial. Network-on-chip exhibits a promising performance for the integration of one FPGA. A sustainable communication architecture requires stable performance as the number of applications or users grows. Wireless network-on-chip has the potential to be that communication architecture, as it boasts the same performance capability as wired solutions in addition to its multicast capacities. We conducted an exploratory study to investiga…
Feasibility of FPGA accelerated IPsec on cloud
2018
Abstract Hardware acceleration for famous VPN solution, IPsec, has been widely researched already. Still it is not fully covered and the increasing latency, throughput, and feature requirements need further evaluation. We propose an IPsec accelerator architecture in an FPGA and explain the details that need to be considered for a production ready design. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in an SDN network. Related work performance rates in 64 byte packet size for throughput is 1–2 Gbps with 0.2 ms latency in software, and 1–4 Gbps with unknown latencies for hardware solutions. Our proposed architecture is capable to host 1000 concurre…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
Multiple register synchronization with a high-speed serial link using the Aurora protocol
2013
In this work, the development and characterization of a multiple synchronous registers interface communicating with a high-speed serial link and using the Aurora protocol is presented. A detailed description of the developing process and the characterization methods and hardware test benches are also included. This interface will implement the slow control busses of the digitizer cards for the second generation of electronics for the Advanced GAmma Tracking Array (AGATA).
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment
2011
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on th…
The Mu3e Data Acquisition
2020
The Mu3e experiment aims to find or exclude the lepton flavour violating decay $\mu^+\to e^+e^-e^+$ with a sensitivity of one in 10$^{16}$ muon decays. The first phase of the experiment is currently under construction at the Paul Scherrer Institute (PSI, Switzerland), where beams with up to 10$^8$ muons per second are available. The detector will consist of an ultra-thin pixel tracker made from High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), complemented by scintillating tiles and fibres for precise timing measurements. The experiment produces about 100 Gbit/s of zero-suppressed data which are transported to a filter farm using a network of FPGAs and fast optical links. On the filte…