Search results for "Gate array"
showing 10 items of 185 documents
A New Embedded Coprocessor for Clifford Algebra based Software Intensive Systems
2011
Computer graphics applications require efficient tools to model geometric objects and their transformations. Clifford algebra (also known as geometric algebra) is receiving a growing attention in many research fields, such as computer graphics, machine vision and robotics, as a new, interesting computational paradigm that offers a natural and intuitive way to perform geometric calculations. At the same time, compute-intensive graphics algorithms require the execution of million Clifford operations. Clifford algebra based software intensive systems need therefore the support of specialized hardware architectures capable of accelerating Clifford operations execution. In this paper the archite…
An Embedded Processor for Metabolic Networks Optimization
2011
In recent years biological processes modelling and simulation have become two key issues in analyzing complex cellular systems. The computational requirements suggest to investigate alternative solutions to the common supercomputers and clusters in order to optimize and overcome computational bottleneck. The goal of this work is the design and the realization of an embedded processor for metabolic networks optimization in order to examine their behaviour and robustness under malfunctions of one or more nodes. The embedded processor has been prototyped on the Celoxica RC203E board, equipped with programmable FPGA technologies. A case studied outlining the E. Coli bacteria metabolic network i…
Design and Implementation of an Efficient Fingerprint Features Extractor
2014
Biometric recognition systems are rapidly evolving technologies and their use in embedded devices for accessing and managing data and resources is a very challenging issue. Usually, they are composed of three main modules: Acquisition, Features Extraction and Matching. In this paper the hardware design and implementation of an efficient fingerprint features extractor for embedded devices is described. The proposed architecture, designed for different acquisition sensors, is composed of four blocks: Image Pre-processor, Macro-Features Extractor, Micro- Features Extractor and Master Controller. The Image Pre- processor block increases the quality level of the input raw image and performs an a…
An Embedded, FPGA-based Computer Graphics Coprocessor with Native Geometric Algebra Support
2009
The representation of geometric objects and their transformation are the two key aspects in computer graphics applications. Traditionally, computer-intensive matrix calculations are involved in modeling and rendering three-dimensional (3D) scenery. Geometric algebra (aka Clifford algebra) is attracting attention as a natural way to model geometric facts and as a powerful analytical tool for symbolic calculations. In this paper, the architecture of Clifford coprocessor (CliffoSor) is introduced. CliffoSor is an embedded parallel coprocessing core that offers direct hardware support to Clifford algebra operators. A prototype implementation on a programmable gate array (FPGA) board is detailed…
A Dual-Core Coprocessor with Native 4D Clifford Algebra Support
2012
Geometric or Clifford Algebra (CA) is a powerful mathematical tool that is attracting a growing attention in many research fields such as computer graphics, computer vision, robotics and medical imaging for its natural and intuitive way to represent geometric objects and their transformations. This paper introduces the architecture of CliffordCoreDuo, an embedded dual-core coprocessor that offers direct hardware support to four-dimensional (4D) Clifford algebra operations. A prototype implementation on an FPGA board is detailed. Experimental results show a 1.6× average speedup of CliffordCoreDuo in comparison with the baseline mono-core architecture. A potential cycle speedup of about 40× o…
Embedded Coprocessors for Native Execution of Geometric Algebra Operations
2016
Clifford algebra or geometric algebra (GA) is a simple and intuitive way to model geometric objects and their transformations. Operating in high-dimensional vector spaces with significant computational costs, the practical use of GA requires dedicated software and/or hardware architectures to directly support Clifford data types and operators. In this paper, a family of embedded coprocessors for the native execution of GA operations is presented. The paper shows the evolution of the coprocessor family focusing on the latest two architectures that offer direct hardware support to up to five-dimensional Clifford operations. The proposed coprocessors exploit hardware-oriented representations o…
A Programmable Networked Processing Node for 3D Brain Vessels Reconstruction
2011
Real-time 3D imaging represents a developing trend in medical imaging. However, most of the 3D medical imaging algorithms are computationally intensive. In this paper, a programmable networked node for 3D brain vessels reconstruction is proposed. Starting from 2D PC-MRA (Phase-Contrast Magnetic Resonance Angiography) sequences, the node is able to generate the 3D brain vasculature using the MIP (Maximum Intensity Projection) algorithm. The node has been prototyped on the Celoxica RC203E board, equipped with a Virtex II FPGA, to get the advantages of an hardware implementation, reaching a better throughput with respect to analogous software implementations. Its generality and programmable ca…
A New Model for Sigma-Delta Modulator Oriented to Digitally Controlled DC/DC Converter
2007
Recent research activities have shown the feasibility and advantages of using digital controller ICs specifically developed for high-frequency switching converters, highlighting a challenging future trend in Switched-mode power supplies (SMPS) applications. Up to a few years ago, the application of digital control for SMPS was impractical due to the high cost and low performance of DSP and microcontroller systems, even if the advantages that digital controllers offer were well known, such as immunity to analog component variations and ability to implement sophisticated control schemes and system diagnostics. Digital controller ICs potentially offer other advantages from the integrated desig…
Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM
2021
This work examines the FPGA programmable logic platforms applied to minimum losses control of a Permanent Magnet Synchronous Motor (PMSM), which represents a flexible solution for the implementation of an advanced digital control algorithm, given their intrinsic parallel structure and the capability to be directly reprogrammable in the field. In particular, design and validation of a FPGA-based Hardware-In-the-Loop (HIL) simulator is proposed, by investigating about data format, quantization and discretization effects and other issues arising during the experimental validation of a controller prototype, in order to reduce the embedded software development cycle and test control systems. The…
Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA
2005
This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost, spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained, based on four partial configurations of arithmetic decoder…