Search results for "Gate array"
showing 10 items of 185 documents
Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs
2002
FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA 's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy, we realized an AT40K40 based board ARDOISE.
Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform
2007
The communication synthesis is the main problematic in the multiprocessor system-on-chip (MPSoC). To resolve this problem, several methodologies can be used. These methodologies require automated methods to specify, generate and optimize the hardware, software, and the architectural interfaces between them. In this paper, we present a methodology flow for hardware-software communication synthesis for multiprocessor system-on-chip platform which are dedicated to streaming applications. Our methodology consists of high level architecture communication synthesis from functional description of the MPSoC design. The solution that we propose consists in synthesizing a custom bus architecture for …
FPGA implementation of Spiking Neural Networks supported by a Software Design Environment
2011
Abstract This paper is focused on the creation of Spiking Neural Networks (SNN) in hardware due to their advantages for certain problem solving and their similarity to biological neural system. One of the main uses of this neural structure is pattern classification. The chosen model for the spiking neuron is the Spike Response Model (SRM). For SNN design and implementation, a software application has been developed to provide easy creation, simulation and automatic generation of the hardware model. VHDL was used for the hardware model. This paper describes the functionality of SNN and the design procedure followed to obtain a working neural system in both software and hardware. Designed VHD…
FPGA implementation of Spiking Neural Networks
2012
Abstract Spiking Neural Networks (SNN) have optimal characteristics for hardware implementation. They can communicate among neurons using spikes, which in terms of logic resources, means a single bit, reducing the logic occupation in a device. Additionally, SNN are similar in performance compared to other neural Artificial Neural Network (ANN) architectures such as Multilayer Perceptron, and others. SNN are very similar to those found in the biological neural system, having weights and delays as adjustable parameters. This work describes the chosen models for the implemented SNN: Spike Response Model (SRM) and temporal coding is used. FPGA implementation using VHDL language is also describe…
Fast spiking neural network architecture for low-cost FPGA devices
2012
Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by arti…
Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC
2019
Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SN…
A novel digital control for DC/DC converters to improve steady-state performances
2006
This paper describes an innovative digital PWM control implementation for low voltage, high current DC-DC converters. The proposed technique, based on the use of a low resolution DAC, improves steady-state performances, minimizing limit cycle effects. The novel technique is tested on a FPGA-based single phase buck converter operating at 250 kHz. A detailed description of the proposed architecture is given and test results, simulation and experimental ones, are shown
The readout system and the trigger algorithm implementation for the UFFO Pathfinder
2012
Since the launch of the SWIFT, Gamma-Ray Bursts (GRBs) science has been much progressed. Especially supporting many measurements of GRB events and sharing them with other telescopes by the Gamma-ray Coordinate Network (GCN) have resulted the richness of GRB events, however, only a few of GRB events have been measured within a minute after the gamma ray signal. This lack of sub-minute data limits the study for the characteristics of the UV-optical light curve of the short-hard type GRB and the fast-rising GRB. Therefore, we have developed the telescope named the Ultra-Fast Flash Observatory (UFFO) Pathfinder, to take the sub-minute data for the early photons from GRB. The UFFO Pathfinder has…
Implementation on NI-SOM sbRIO-9651 and Experimental Validation of Multi-Carrier PWM Techniques for Three-Phase Five Level Cascaded H-Bridge Inverter
2021
Multilevel Power Inverters (MPIs) represent a valid solution to improve the performances of energy production systems from renewable energy sources. Furthermore, the use of novel FPGA control systems allows simplifying the implementation of multicarrier PWM techniques for MPIs with computational benefits. This paper describes the implementation of several multicarrier PWM techniques on NI-SOM sbRIO-9651 for the control of a three-phase five-level cascaded H-bridge inverter. In detail, sbRIO-9651 is a control system in the field of Power Electronics and Drives (PED) programmable in the LabVIEW graphical programming environment. The paper is focused on modulation techniques implementation, te…
A simple timestamping data acquisition system for ToF-ERDA
2015
A new data acquisition system, ToF-DAQ, has been developed for a ToF-ERDA telescope and other ToF-E and ToF-ToF measurement systems. ToF-DAQ combines an analogue electronics front-end to asynchronous time stamped data acquisition by means of a FPGA device. Coincidences are sought solely in software based on the timestamps. Timestamping offers more options for data analysis as coincidence events can be built also in offline analysis. The system utilises a National Instruments R-series FPGA device and a Windows PC as a host computer. Both the FPGA code and the host software were developed using the National Instruments LabVIEW graphical programming environment. Up to eight NIM ADCs can be han…