Search results for "Gate array"

showing 10 items of 185 documents

Latest Frontier Technology and Design of the ATLAS Calorimeter Trigger Board Dedicated to Jet Identification for the LHC Run 3

2016

To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the “A Toroidal LHC ApparatuS” (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which each use different physics objects for the trigger selection. The article focusses on the jet Feature EXtractor (jFEX) prototype, one of the three types of Feature Extractors. Up to 2 TB/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget.…

EngineeringLarge Hadron ColliderCalorimeter (particle physics)010308 nuclear & particles physicsbusiness.industryPhysics::Instrumentation and DetectorsElectrical engineeringLatency (audio)01 natural sciencesSignal030218 nuclear medicine & medical imaging03 medical and health sciences0302 clinical medicineUpgrade0103 physical sciencesMulti-gigabit transceiverSignal integritybusinessField-programmable gate arrayParticle Physics - Experiment
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Commissioning Experience with the ATLAS Level-1 Calorimeter Trigger System

2007

The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects and energy sums. The production of final modules started in 2006, and installation of these modules and the necessary infrastructure…

EngineeringLarge Hadron ColliderIntegration testingbusiness.industryPhysics::Instrumentation and DetectorsReal-time computingATLAS experimentFull scaleCalorimeterData flow diagramNuclear electronicsDetectors and Experimental TechniquesField-programmable gate arraybusiness
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Technical and economical evaluation on the use of reconfiguration systems in some EU countries for PV plants

2017

This paper shows the technical and economical evaluation of the application of a reconfiguration system for photovoltaic (PV) plants, considering the incentives system in some European Union countries. The reconfiguration system is an alternative to the distributed maximum power point tracking technique which used to increase the power production in the PV plants under the mismatch phenomenon. The reconfiguration techniques employ a microprocessor-based or field-programmable gate array-based system that modifies the layout of the PV plant through the change of the connections among modules. After having presented the main features working of the PV reconfiguration system allowing the improv…

EngineeringPartial shading (PS)020209 energy02 engineering and technologySettore ING-IND/32 - Convertitori Macchine E Azionamenti ElettriciIndustrial and Manufacturing EngineeringMaximum power point trackingGate arrayIncentives policie0202 electrical engineering electronic engineering information engineeringProduction (economics)media_common.cataloged_instancePV system topologyElectrical and Electronic EngineeringEuropean unionPhotovoltaic (PV) power systemmedia_commonMismatch lossebusiness.industryMismatch conditionPhotovoltaic systemControl reconfigurationControl engineeringInvestment (macroeconomics)Reliability engineeringSettore ING-IND/31 - ElettrotecnicaIncentiveControl and Systems EngineeringReconstructionbusinessSettore ING-INF/07 - Misure Elettriche E Elettroniche
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An FPGA-Based Software Defined Radio Platform for the 2.4GHz ISM Band

2006

A prototype of a Software Defined Radio (SDR) platform has been successfully designed and tested implementing a reconfigurable IEEE 802.11 and ZigBee receiver. The system exploits the reconfiguration capability of an FPGA for implementing a number of receiver configurations that share the same RF front-end. Configurations can be switched at run time, or can share the available logic and radio resource.

EngineeringRF front endRadio receiver designExploitbusiness.industrySoftware radioComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKSFrequency shift keyingControl reconfigurationSoftware-defined radioRemote radio headEmbedded systemField-programmable gate arraybusinessISM bandreceived signal
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Heavy ion SEE test of 2 Gbit DDR3 SDRAM

2011

New generation 2 Gbit DDR3 SDRAMs from Micron, Samsung and Nanya have been tested under heavy ions. SEFIs significantly outweigh random SEU errors even at low LET; however, SEFIs can be mitigated by frequent re-initialization.

EngineeringSingle event upsetGigabitbusiness.industryElectronic engineeringOptoelectronicsHeavy ionbusinessField-programmable gate arrayDDR3 SDRAM2011 12th European Conference on Radiation and Its Effects on Components and Systems
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<title>Architecture for real-time wood inspection</title>

2000

This study has been realized to improve industrial machines that allow to analyze planks by detecting their width and too important defects thanks to a computer vision system. These machines are currently piloted by software with the help of PCs. The aim of our work is to realize a hardware card to increase the processing speed.

EngineeringSoftwarebusiness.industryEmbedded systemSystems architectureImage processingArchitecturebusinessField-programmable gate arrayEdge detectionSPIE Proceedings
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Compact instrumentation for radiation tolerance test of flash memories in space environment

2010

Aim of this work is the description of a test equipment, designed to be integrated on board of a microsatellite, able to investigate the radiation tolerance of non-volatile memory arrays in a real flight experiment. An FPGA-based design was adopted to preserve a high flexibility degree. Besides standard Program/Read/Erase functions, additional features such as failure data screening and latch-up protection have been implemented. The instrument development phase generated, as a by-product, a non-rad-hard version of the instrument that allowed performing in-situ experiments using 60Co and 10 MeV Boron irradiation facilities on Ground. Preliminary measurement results are reported to show the i…

EngineeringTolerance analysisbusiness.industrySystem testingSettore ING-INF/01 - ElettronicaFlash memorySpace equipmentNon-volatile memoryNon-volatile memoryFPGA-based instrumentationRadiation hardneInstrumentation (computer programming)businessField-programmable gate arrayRadiation hardeningInstrumentationComputer hardwareSpace environment
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Design and testing of the high speed signal densely populated ATLAS calorimeter trigger board dedicate to jet identification

2017

Abstract—The ATLAS experiment has planned a major upgrade in view of the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2021. As part of this, the trigger at Level-1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (three in total), which each uses different physics objects for the trigger selection. The contribution focusses on the jet Feature EXtractor (jFEX) prototype. Up to a data volume of 2 TB/s has to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. Such requirements translate …

EngineeringUpgradeLarge Hadron ColliderCalorimeter (particle physics)business.industryGigabitATLAS experimentElectrical engineeringSignal integrityTransceiverbusinessField-programmable gate arrayParticle Physics - Experiment
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Reconfigurable digital instrumentation based on FPGA

2004

A novel application of FPGA to realize digital test equipment is proposed. It takes advantage of the dynamic reconfigurability of FPGAs so easily tailoring custom test functions in the same instrument. This results in high effective, compact and low cost instruments.

Engineeringbusiness.industryDigital instrumentationReconfigurabilityIntegrated circuit designFPGA reconfigurable systems instrumentationSettore ING-INF/01 - ElettronicaProgrammable logic arrayReconfigurable computingProgrammable logic deviceAutomatic test equipmentEmbedded systemHardware_ARITHMETICANDLOGICSTRUCTURESbusinessField-programmable gate array
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Development of an optical link card for the upgrade phase II of TileCal experiment

2010

This work presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment as part of the evaluation of different technologies for the final choice in the next two years. The board is designed as a mezzanine which can work independently or plugged in the Optical Multiplexer Board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gbps and one SFP optical connector for lower speeds and compatibility with existing hardware as the Read Out Driver. All processing is done in a Stratix II GX FPGA. Details are given on the hardware design including signal and …

Engineeringbusiness.industryFirmwareOptical linkPower integritycomputer.software_genreMultiplexerUpgradeEmbedded systemStratixTransceiverbusinessField-programmable gate arraycomputerComputer hardware2010 17th IEEE-NPSS Real Time Conference
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