Search results for "Gate array"
showing 10 items of 185 documents
Resource-efficient hardware implementation of a neural-based node for automatic fingerprint classification
2017
Modern mobile communication networks and Internet of Things are paving the way to ubiquitous and mobile computing. On the other hand, several new computing paradigms, such as edge computing, demand for high computational capabilities on specific network nodes. Ubiquitous environments require a large number of distributed user identification nodes enabling a secure platform for resources, services and information management. Biometric systems represent a useful option to the typical identification systems. An accurate automatic fingerprint classification module provides a valuable indexing scheme that allows for effective matching in large fingerprint databases. In this work, an efficient em…
Improvement of Fingerprint Sensor Reading Using FPGA Devices
2008
In order to realize fingerprint recognition system in real time environment, we describe in this paper signal controller to read fingerprint sensor generated in FPGA devices. Basically this signal is generated using state machine. The simulation result for behavioral simulation and signal generation read by logic analyzer are presented in this paper. Initialization and reading time for 76800 pixels are 50.99 mS. It is faster than fingerprint sensor using USB connection, which is more than 250 ms.
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems
2017
Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
Hardware implementation of content based video indexing algorithms
2005
This paper focus on hardware implementation of content based video indexing techniques by using the FPGA technology. We aim to propose hardware modules that can satisfy requirements of constrained applications, such as real time applications and complex applications that can combine a large number of techniques in the same indexing system. We represent tow examples of micro-architectures related to the dominant colors descriptor and the compact color descriptor.
Accelerating bioinformatics applications via emerging parallel computing systems [Guest editorial]
2015
The papers in this issue focus on advanced parallel computing systems for bioinformatics applications. This papers provide a forum to publish recent advances in the improvement of handling bioinformatics problems on emerging parallel computing systems. These systems can be characterized by exploiting different types of parallelism, including fine-grained versus coarse-grained and thread-level parallelism versus datalevel parallelism versus request-level parallelism. Hence, parallel computing systems based on multi- and many-core CPUs, many-core GPUs, vector processors, or FPGAs offer the promise to massively accelerate many bioinformatics algorithms and applications, ranging from computeint…
Hardware implementation of real-time Extreme Learning Machine in FPGA: Analysis of precision, resource occupation and performance
2016
Extreme Learning Machine (ELM) on-chip learning is implemented on FPGA.Three hardware architectures are evaluated.Parametrical analysis of accuracy, resource occupation and performance is carried out. Display Omitted Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. Its hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training…
A novel hardware accelerator for the HEVC intra prediction
2015
International audience; A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 10…
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction
2016
International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…
A readout unit for high rate applications
2002
The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…
Reconstruction of Micropattern Detector Signals using Convolutional Neural Networks
2017
Micropattern gaseous detector (MPGD) technologies, such as GEMs or MicroMegas, are particularly suitable for precision tracking and triggering in high rate environments. Given their relatively low production costs, MPGDs are an exemplary candidate for the next generation of particle detectors. Having acknowledged these advantages, both the ATLAS and CMS collaborations at the LHC are exploiting these new technologies for their detector upgrade programs in the coming years. When MPGDs are utilized for triggering purposes, the measured signals need to be precisely reconstructed within less than 200 ns, which can be achieved by the usage of FPGAs. In this work, we present a novel approach to id…