Search results for "Gate"
showing 10 items of 1811 documents
Shift-and-scale-invariant pattern recognition using an elliptic coordinate-transformed phase-only filter
1992
A shift-and-scale-invariant elliptic coordinate-transformed phase-only filter in proposed. The filter is built in three steps: the complex conjugate of a basic-size target spectrum is calculated, its phase-only part is taken, and then the elliptic coordinate transformation is made. In the extreme case the scale ratio of recognizable objects equals 1:1.5, permitting good recognition of object sizes S within the range 0.83/= S/= 1.25. Discrimination abilities and relative Horner efficiencies of a few versions of the filter are calculated.
Shift and scale-invariant correlator using a radially stretched phase-only filter
1995
A radial stretching of the phase only filter depending on the energy angular distribution of the target spectrum is used to perform shift and scale invariant pattern recognition. The complex conjugate of a basic size target Fourier transform and the cumulative energy angular distribution are calculated. Then the radially stretched filter providing the same energy contribution to the correlation peak independent on the target size is prepared and used in a conventional correlator, with spherical-wave illumination. The maximum scale ratio of recognizable objects equals 1:1.5. Computer simulations and experimental results, showing the performance of the filter are presented.
Energy-efficient quantum computing
2016
In the near future, a major challenge in quantum computing is to scale up robust qubit prototypes to practical problem sizes and to implement comprehensive error correction for computational precision. Due to inevitable quantum uncertainties in resonant control pulses, increasing the precision of quantum gates comes with the expense of increased energy consumption. Consequently, the power dissipated in the vicinity of the processor in a well-working large-scale quantum computer seems unacceptably large in typical systems requiring low operation temperatures. Here, we introduce a method for qubit driving and show that it serves to decrease the single-qubit gate error without increasing the a…
Moving Learning Machine Towards Fast Real-Time Applications: A High-Speed FPGA-based Implementation of the OS-ELM Training Algorithm
2018
Currently, there are some emerging online learning applications handling data streams in real-time. The On-line Sequential Extreme Learning Machine (OS-ELM) has been successfully used in real-time condition prediction applications because of its good generalization performance at an extreme learning speed, but the number of trainings by a second (training frequency) achieved in these continuous learning applications has to be further reduced. This paper proposes a performance-optimized implementation of the OS-ELM training algorithm when it is applied to real-time applications. In this case, the natural way of feeding the training of the neural network is one-by-one, i.e., training the neur…
SDN@home: A Method for Controlling Future Wireless Home Networks
2016
Recent advances in wireless networking technologies are leading toward the proliferation of novel home network applications. However, the landscape of emerging scenarios is fragmented due to their varying technological requirements and the heterogeneity of current wireless technologies. We argue that the development of flexible software-defined wireless architectures, including such efforts as the wireless MAC processor, coupled with SDN concepts, will enable the support of both emerging and future home applications. In this article, we first identify problems with managing current home networks composed of separate network segments governed by different technologies. Second, we point out t…
An efficient hardware implementation of MQ decoder of the JPEG2000
2014
Abstract JPEG2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG2000 standard has not only better not only has better compression ratios, but it also offers some exciting features. As it’s hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The MQ decoder of the JPEG2000 standard is an important bottleneck for real-time applications. In order to meet the real-time requirement we propose in this paper a novel architecture for a MQ decoder with high throughput which is comparable to tha…
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
SVM approximation for real-time image segmentation by using an improved hyperrectangles-based method
2003
A real-time implementation of an approximation of the support vector machine (SVM) decision rule is proposed. This method is based on an improvement of a supervised classification method using hyperrectangles, which is useful for real-time image segmentation. The final decision combines the accuracy of the SVM learning algorithm and the speed of a hyperrectangles-based method. We review the principles of the classification methods and we evaluate the hardware implementation cost of each method. We present the combination algorithm, which consists of rejecting ambiguities in the learning set using SVM decision, before using the learning step of the hyperrectangles-based method. We present re…
Modeling RISC-V Processor in IP-XACT
2018
IP-XACT is the most used standard in IP (Intellectual Property) integration. It is intended as a language neutral golden reference, from which RTL and HW dependent SW is automatically generated. Despite its wide popularity in the industry, there are practically no public and open design examples for any part of the design flow from IP-XACT to synthesis. One reason is the difficulty of creating IP-XACT models for existing RTL projects. In this paper, we address the issues by modeling the PULPino RISC-V microprocessor that is written in SystemVerilog (SV) and the project distributed over several repositories. We propose how to solve the mismatching concepts between SV project and IP-XACT, and…
Efficient FPGA Implementation of an Adaptive Noise Canceller
2006
A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.