Search results for "Hard"

showing 10 items of 2294 documents

Annales des travaux des auditeurs de l'IHEDN 2006 : "Amérique latine : émergence d'un pôle"

2006

CD rom; International audience

Hardware_MEMORYSTRUCTURESIHEDN[ SHS.HIST ] Humanities and Social Sciences/History[SHS.HIST] Humanities and Social Sciences/Historyanales[ SHS ] Humanities and Social Sciences[SHS] Humanities and Social SciencesauditeursHardware_CONTROLSTRUCTURESANDMICROPROGRAMMING[SHS.HIST]Humanities and Social Sciences/HistoryAmérique latineComputingMilieux_MISCELLANEOUS[SHS]Humanities and Social Sciences
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Annales des travaux des auditeurs de l'IHEDN 2006 : "Mers et océans : défis européens et mondiaux"

2006

CD rom; International audience

Hardware_MEMORYSTRUCTURESIHEDN[ SHS.HIST ] Humanities and Social Sciences/Historymers et océans[SHS.HIST] Humanities and Social Sciences/Historyanales[ SHS ] Humanities and Social Sciences[SHS] Humanities and Social SciencesauditeursHardware_CONTROLSTRUCTURESANDMICROPROGRAMMING[SHS.HIST]Humanities and Social Sciences/HistoryComputingMilieux_MISCELLANEOUS[SHS]Humanities and Social Sciences
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kmcEx

2019

Memory-frugal and retrieval-efficient encoding of counted k-mers.

Hardware_MEMORYSTRUCTURESInformationSystems_INFORMATIONSTORAGEANDRETRIEVALSequencingData_CODINGANDINFORMATIONTHEORY
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Comparison of TID response and SEE characterization of single- and multi-level high density NAND flash memories

2009

Heavy ion single-event measurements and total ionizing dose (TID) response for 8Gb commercial NAND flash memories are reported. Radiation results of multilevel flash technology are compared with results from single-level flash technology. The single-level devices are less sensitive to single event upsets (SEUs) than multi-level devices. In general, these commercial high density memories exhibit less TID degradation compared to older generations of flash memories. The charge pump in this study survived up to 600 krads.

Hardware_MEMORYSTRUCTURESMaterials sciencebusiness.industryNAND gateFlash memoryNon-volatile memoryFlash (photography)Single event upsetAbsorbed doseComputer data storageCharge pumpElectronic engineeringOptoelectronicsbusiness2009 European Conference on Radiation and Its Effects on Components and Systems
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Parallel macro pipelining on the intel SCC many-core computer

2013

In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data after it finishes its work. Our case-study is a parallel rendering system which renders successive images and applies different filters on them. On normal graphics adapters this is usually done in multiple cycles, we do this in a single pipeline pass. We show that we can achieve a significant speedup by using multiple parallel pipelines on t…

Hardware_MEMORYSTRUCTURESSpeedupParallel renderingbusiness.industryComputer sciencePipeline (computing)020207 software engineering02 engineering and technologyParallel computingGraphics pipelineSingle-chip Cloud ComputerMemory bankParallel processing (DSP implementation)Embedded system0202 electrical engineering electronic engineering information engineeringMacrobusiness
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Simple method for limiting delay of optimized interleavers for turbo-codes

2000

An iterative interleaver growth algorithm is extended to allow the delay and required memory of designed interleavers to be halved with negligible performance loss. The original algorithm is efficient for two-component parallel concatenated turbo-codes with given constituent encoders that are optimum with regard to a cost function satisfying some mild conditions. However, it is only actually optimum if the selected set of patterns is representative of low-weight turbo-codewords. The new interleaver uses all terminating error patterns having an input weight not greater than a fixed IWX and single-coder output weight not greater than WX is proposed.

Hardware_MEMORYSTRUCTURESTheoretical computer sciencedelaysSettore ING-INF/03 - TelecomunicazioniLimitingSimple extensionconcatenated codePermutationSimple (abstract algebra)turbo codeTurbo codeFinite stateElectrical and Electronic EngineeringAlgorithmMathematics
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Extending SSD lifetime in database applications with page overwrites

2013

Flash-based Solid State Disks (SSDs) have been a great success story over the last years and are widely used in embedded systems, servers, and laptops.One often overlooked ability of NAND flash is that flash pages can be overwritten in certain circumstances. This can be used to decrease wear out and increase performance.In this paper, we analyze the potential of overwrites for the most used data structure in database applications: the B-Tree. We show that with overwrites it is possible to significantly reduce flash wear out and increase overall performance.

Hardware_MEMORYSTRUCTURESWear outDatabaseComputer scienceSolid-stateNAND gatecomputer.software_genreData structureFlash (photography)ServerOperating systemOverall performancecomputerFlash file systemProceedings of the 6th International Systems and Storage Conference on - SYSTOR '13
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Annales des travaux des auditeurs de l'IHEDN 2007 : "La mondialisation : chance ou menace pour l'Europe et la France ?"

2007

CD rom; International audience

Hardware_MEMORYSTRUCTURES[ SHS.HIST ] Humanities and Social Sciences/HistoryAmérique latine[SHS]Humanities and Social SciencesIHEDN[SHS.HIST] Humanities and Social Sciences/History[ SHS ] Humanities and Social Sciencesmondialisation[SHS] Humanities and Social SciencesauditeursFranceHardware_CONTROLSTRUCTURESANDMICROPROGRAMMING[SHS.HIST]Humanities and Social Sciences/HistoryComputingMilieux_MISCELLANEOUS
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Annales des travaux des auditeurs de l'IHEDN 2009 : "L'Union européenne en quête de sécurité extérieure et de sécurité intérieure"

2009

CD rom; International audience

Hardware_MEMORYSTRUCTURES[ SHS.HIST ] Humanities and Social Sciences/Historysécurité intérieure[SHS]Humanities and Social SciencesIHEDN[SHS.HIST] Humanities and Social Sciences/History[ SHS ] Humanities and Social Sciences[SHS] Humanities and Social Sciencessécurité extérieureauditeursHardware_CONTROLSTRUCTURESANDMICROPROGRAMMINGUnion européenne[SHS.HIST]Humanities and Social Sciences/HistoryComputingMilieux_MISCELLANEOUS
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Additional file 4: of RIP-Chip analysis supports different roles for AGO2 and GW182 proteins in recruiting and processing microRNA targets

2019

Overview of gene expression levels in IP and FT samples. Focus on the enriched genes in AGO2-IP and GW182-IP vs FT samples. The reported expression levels are computed as the average values of the three performed experimental replicates. (PDF 1423 kb)

Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION
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