Search results for "Hardware architecture"
showing 10 items of 120 documents
LDR Image to HDR Image Mapping with Overexposure Preprocessing
2013
International audience; Due to the growing popularity of High Dynamic Range (HDR) images and HDR displays, a large amount of existing Low Dynamic Range (LDR) images are required to be converted to HDR format to benefit HDR advantages, which give rise to some LDR to HDR algorithms. Most of these algorithms especially tackle overexposed areas during expanding, which is the potential to make the image quality worse than that before processing and introduces artifacts. To dispel these problems, we . present a new,LDR to HDR approach, unlike the existing techniques, it focuses on avoiding sophisticated treatment to overexposed areas in dynamic range expansion step. Based on a separating principl…
City gates of Augustodunum and their architectural models (Gaul, Italy, Western Provinces of the Roman Empire)
2013
Augustodunum, civitas Aeduorum, roman city founded under the reign of Augustus, was equipped with four roman city gates : the gate of Arroux and the gate of Saint André, both well preserved, the gate of Saint Andoche which sole remaining part is a flanking tower, and the gate of Rome, destroyed long ago.The heart of this study lies in the stratigraphic reading of those gates structure and in thoughts about the building site of Autun’s city gates operating process. Moreover, since the 16th century, antiquaries, travelers and artists have described in many ways their visits to the roman city gates of Autun. These accounts constitute a major documentary collection of written and iconographical…
Fast and Robust Face Detection on a Parallel Optimized Architecture implemented on FPGA
2009
In this paper, we present a parallel architecture for fast and robust face detection implemented on FPGA hardware. We propose the first implementation that meets both real-time requirements in an embedded context and face detection robustness within complex backgrounds. The chosen face detection method is the Convolutional Face Finder (CFF) algorithm, which consists of a pipeline of convolution and subsampling operations, followed by a multilayer perceptron. We present the design methodology of our face detection processor element (PE). This methodology was followed in order to optimize our implementation in terms of memory usage and parallelization efficiency. We then built a parallel arch…
Design of a Real-time face detection parallel architecture using High-Level Synthesis
2008
Abstract We describe a High-Level Synthesis implementation of a parallel architecture for face detection. The chosen face detection method is the well-known Convolutional Face Finder (CFF) algorithm, which consists of a pipeline of convolution operations. We rely on dataflow modelling of the algorithm and we use a high-level synthesis tool in order to specify the local dataflows of our Processing Element (PE), by describing in C language inter-PE communication, fine scheduling of the successive convolutions, and memory distribution and bandwidth. Using this approach, we explore several implementation alternatives in order to find a compromise between processing speed and area of the PE. We …
Multi-Kernel Implicit Curve Evolution for Selected Texture Regions Segmentation in VHR Satellite Images
2014
Very high resolution (VHR) satellite images provide a mass of detailed information which can be used for urban planning, mapping, security issues, or environmental monitoring. Nevertheless, the processing of this kind of image is timeconsuming, and extracting the needed information from among the huge quantity of data is a real challenge. For some applications such as natural disaster prevention and monitoring (typhoon, flood, bushfire, etc.), the use of fast and effective processing methods is demanded. Furthermore, such methods should be selective in order to extract only the information required to allow an efficient interpretation. For this purpose, we propose a texture region segmentat…
Network architectures and energy efficiency for high performance data centers
2017
The increasing trend to migrate applications, computation and storage into more robust systems leads to the emergence of mega data centers hosting tens of thousands of servers. As a result, designing a data center network that interconnects this massive number of servers, and providing efficient and fault-tolerant routing service are becoming an urgent need and a challenge that will be addressed in this thesis. Since this is a hot research topic, many solutions are proposed like adapting new interconnection technologies and new algorithms for data centers. However, many of these solutions generally suffer from performance problems, or can be quite costly. In addition, devoted efforts have n…
Preliminary study on the design of a low-cost movement analysis system: reliability measurement of Timed Up and Go test
2014
International audience; In this paper, we present experiments on the design of a novel movement analysis system for real-time balance assessment in the frail elderly. Using the Microsoft Kinect sensors, we capture TUG (Timed Up and Go) tests and analyze mainly the transfer from sitting-to-standing and back-to-sitting which represent two of the most commonly executed human movements. Nine spatio-temporal parameters were extracted from recorded joint positions by 3D skeletal sequence processing. In order to validate and evaluate the developed system, practical test experiences have been performed on ten healthy young subjects, who were asked to realize the TUG in three different conditions: n…
VLIW architecture compilation-simulation and its implementation into FPGA
2011
International audience; Embedded systems present a tremendous opportunity to customize designs by exploiting the application behavior. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures achievement of these constraint. In the recent years, these systems have grown to the new concepts with inner computing processing for improving the performance that will be known as embedded computing system. Embedded computing with VLIW (Very Long Instruction Word) based architecture has been alternative choice to implement the target application into electronics devices in many areas such as digital image p…
A Robust Color Circle-Marker Detection Algorithm based on Color information and Hough Transformation
2009
International audience
Modular VLIW processor based on FPGA for real-time image processing
2011
National audience