Search results for "Hardware architecture"
showing 10 items of 120 documents
Chip-to-chip plasmonic interconnects and the activities of EU project NAVOLCHI
2012
In this paper, the chip-to-chip interconnection architecture adopted by the EU-project NAVOLCHI are discussed. The plasmonic physical layer consisting of a plasmonic nanoscale laser, a modulator, an amplifier and a detector is introduced. Current statuses of the plasmonic devices are reviewed.
Surface plasmon circuitry in opto-electronics
2012
This tutorial reviews the physics of surface plasmon circuitry in order to bring to the fore recently demonstrated applications of surface plasmon in optoelectronics such as on-board optical interconnects or routing in datacom networks.
Steering between level repulsion and attraction: broad tunability of two-port driven cavity magnon-polaritons
2019
Abstract Cavity-magnon polaritons (CMPs) are the associated quasiparticles of the hybridization between cavity photons and magnons in a magnetic sample placed in a microwave resonator. In the strong coupling regime, where the macroscopic coupling strength exceeds the individual dissipation, there is a coherent exchange of information. This renders CMPs as promising candidates for future applications such as in information processing. Recent advances on the study of the CMP now allow not only for creation of CMPs on demand, but also for tuning of the coupling strength—this can be thought of as the enhancement or suppression of information exchange. Here, we go beyond standard single-port dri…
Design environment for hardware generation of SLFF neural network topologies with ELM training capability
2015
Extreme Learning Machine (ELM) is a noniterative training method suited for Single Layer Feed Forward Neural Networks (SLFF-NN). Typically, a hardware neural network is trained before implementation in order to avoid additional on-chip occupation, delay and performance degradation. However, ELM provides fixed-time learning capability and simplifies the process of re-training a neural network once implemented in hardware. This is an important issue in many applications where input data are continuously changing and a new training process must be launched very often, providing self-adaptation. This work describes a general SLFF-NN design environment to assist in the definition of neural netwo…
Perturbative treatment of spin-orbit coupling within spin-free exact two-component theory.
2014
This work deals with the perturbative treatment of spin-orbit-coupling (SOC) effects within the spin-free exact two-component theory in its one-electron variant (SFX2C-1e). We investigate two schemes for constructing the SFX2C-1e SOC matrix: the SFX2C-1e+SOC [der] scheme defines the SOC matrix elements based on SFX2C-1e analytic-derivative theory, hereby treating the SOC integrals as the perturbation; the SFX2C-1e+SOC [fd] scheme takes the difference between the X2C-1e and SFX2C-1e Hamiltonian matrices as the SOC perturbation. Furthermore, a mean-field approach in the SFX2C-1e framework is formulated and implemented to efficiently include two-electron SOC effects. Systematic approximations …
A simple quantum gate with atom chips
2005
We present a simple scheme for implementing an atomic phase gate using two degrees of freedom for each atom and discuss its realization with cold rubidium atoms on atom chips. We investigate the performance of this collisional phase gate and show that gate operations with high fidelity can be realized in magnetic traps that are currently available on atom chips.
An integrated calibration system for liquid argon calorimetry
1999
Abstract A novel technical solution for an integrated version of the pulse generator of a calibration system for liquid argon calorimeters is presented. It consists of a differential amplifier with automatic offset compensation, a current mirror and a switching logic. These components are integrated on an ASIC chip in CMOS technology. The technical realisation as well as results on the performance are presented.
Microwave potentials and optimal control for robust quantum gates on an atom chip
2006
We propose a two-qubit collisional phase gate that can be implemented with available atom chip technology, and present a detailed theoretical analysis of its performance. The gate is based on earlier phase gate schemes, but uses a qubit state pair with an experimentally demonstrated, very long coherence lifetime. Microwave near-fields play a key role in our implementation as a means to realize the state-dependent potentials required for conditional dynamics. Quantum control algorithms are used to optimize gate performance. We employ circuit configurations that can be built with current fabrication processes, and extensively discuss the impact of technical noise and imperfections that charac…
Fast SWAP gate by adiabatic passage
2005
We present a process for the construction of a SWAP gate which does not require a composition of elementary gates from a universal set. We propose to employ direct techniques adapted to the preparation of this specific gate. The mechanism, based on adiabatic passage, constitutes a decoherence-free method in the sense that spontaneous emission and cavity damping are avoided.
Quantum Nondemolition Gate Operations and Measurements in Real Time on Fluctuating Signals
2017
We demonstrate an optical quantum nondemolition (QND) interaction gate with a bandwidth of about 100 MHz. Employing this gate, we are able to perform QND measurements in real time on randomly fluctuating signals. Our QND gate relies on linear optics and offline-prepared squeezed states. In contrast to previous demonstrations on narrow sideband modes, our gate is compatible with quantum states temporally localized in a wave-packet mode including non-Gaussian quantum states. This is the cornerstone of realizing quantum error correction and universal gate operations.