Search results for "Large"

Implementation and performance of the ATLAS second level jet trigger

2008

ATLAS is one of the four major LHC experiments, designed to cover a wide range of physics topics. In order to cope with a rate of 40 MHz and 25 interactions per bunch crossing, the ATLAS trigger system is divided in three different levels. The first one (LVL1, hardware based) identifies signatures in 2 microseconds that are confirmed by the the following trigger levels (software based). The Second Level Trigger (LVL2) only looks at a region of the space around the LVL1 signature (called Region of Interest or ROI), confirming/rejecting the event in about 10 ms, while the Event Filter (Third Level Trigger, EF) has potential full event access and larger processing times, of the order of 1 s. T…

The Upgrade of the ATLAS Level-1 Central Trigger Processor

2013

The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors as well as other sources and makes the final Level-1 Accept (L1A) decision. Due to the increasing luminosity of the LHC and the growing demands of physics and monitoring placed on the ATLAS Level-1 trigger system, the current CTP has reached its design limits. Therefore and in order to provide some margin for future operation, the CTP will be upgraded during the LHC shutdown of 2013/14.

Co-activation of VEGF and NMDA receptors promotes synaptic targeting of AMPA receptors

2016

Light Curves of Radio Supernovae

2007

We present the results from the on-going radio monitoring of recent type II supernovae (SNe), including SNe 2004et, 2004dj, 2002hh, 2001em, and 2001gd. Using the Very Large Array to monitor these supernovae, we present their radio light-curves. From these data we are able to discuss parameterizations and modeling and make predictions of the nature of the progenitors based on previous research. Derived mass loss rates assume wind-established circumstellar medium, shock velocity ~10,000 km/s, wind velocity ~10 km/s, and CSM Temperature ~10,000 K.

Simultaneous radio and X-ray observations of the low-mass X-ray binary GX 13+1

2004

We present the results of two simultaneous X-ray/radio observations of the low-mass X-ray binary GX 13+1, performed in July/August 1999 with the Rossi X-ray Timing Explorer and the Very Large Array. In X-rays the source was observed in two distinct spectral states; a soft state, which had a corresponding 6 cm flux density of ~0.25 mJy, and a hard state, which was much brighter at 1.3-7.2 mJy. For the radio bright observation we measured a delay between changes in the X-ray spectral hardness and the radio brightness of ~40 minutes, similar to what has been found in the micro-quasar GRS 1915+105. We compare our results with those of GRS 1915+105 and the atoll/Z-type neutron star X-ray binarie…

Radio Emission from SN 2001gd in NGC 5033

2003

We present the results of monitoring the radio emission from the Type IIb supernova SN 2001gd between 2002 February 8 and 2002 October 28. Most of the data were obtained using the Very Large Array at the five wavelengths of $\lambda \lambda$1.3 cm (22.4 GHz), 2.0 cm (14.9 GHz), 3.6 cm (8.44 GHz), 6.2 cm (4.86 GHz), and 21 cm (1.4 GHz). Observations were also made with Giant Meterwave Radio Telescope at $\lambda$21 cm (1.4 GHz). The object was discovered optically well after maximum light, making any determination of the early radio evolution difficult. However, subsequent observations indicate that the radio emission has evolved regularly in both time and frequency and is well described by …

Implementation of compact VLSI FitzHugh-Nagumo neurons

2008

In this paper we show a low power and very compact VLSI implementation of a FitzHugh-Nagumo neuron for large network implementations. The circuit consists of only 17 small transistors and two capacitors and consumes less than 23 muW. It is composed of a nonlinear resistor and a lossy active inductor. We demonstrate that a simple low Q active inductor can be used instead of a complex one because the parasitic series resistor can be easily embedded to the FitzHugh-Nagumo model. We also perform a statistical analysis to check the robustness of the circuit against mismatch.

The PAPIA system

1991

In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operatio…

Realistic model of compact VLSI FitzHugh–Nagumo oscillators

2013

In this article, we present a compact analogue VLSI implementation of the FitzHugh–Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off freque…

Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems

2006

Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a great promise by enabling those techniques to execute models faster. This paper focuses on how run-time reconfiguration techniques can be used for emulating the occurrence of transient faults in VLSI models. Although the use of FPGAs for that purpose has been restricted so far to the well-known bit-flip fault model, recent studies in fault repres…