Search results for "Microprocessor"
showing 10 items of 21 documents
An architecture Wi-fi and GPRS for efficient management of distribution electrical networks
2008
In this paper, a telecommunication infrastructure for faults management is proposed. The complete automation of the electrical energy distribution requires the implementation of suitable data transmission systems able to easily interface with microprocessor based systems and to handle large amount of data. In particular, reliability and speed of the data transmission system are required in the fault diagnosis and post-fault management procedures, in order to guarantee high quality standards. The proposed diagnostic system indeed works by means of a set of intercommunicating MV/LV dasiaintelligent substationspsila. In this paper, after a brief description of the fault diagnostic system, an o…
Exploring FPGA‐Based Lock‐In Techniques for Brain Monitoring Applications
2017
Functional near‐infrared spectroscopy (fNIRS) systems for e‐health applications usually suffer from poor signal detection, mainly due to a low end‐to‐end signal‐to‐noise ratio of the electronics chain. Lock‐in amplifiers (LIA) historically represent a powerful technique helping to improve performance in such circumstances. In this work a digital LIA system, based on a Zynq® field programmable gate array (FPGA) has been designed and implemented, in an attempt to explore if this technique might improve fNIRS system performance. More broadly, FPGA‐based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and its …
A readout unit for high rate applications
2002
The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…
The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance
2012
The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS fi…
Management and Control of the Read Out Processors (tpps) of the Aleph Time Projection Chamber
1989
The readout of the Aleph time projection chamber (TPC) relies on a set of 72 time projection processors (TPPs), which are based on a Motorola 68020 microprocessor running a real-time operating system. The advanced processing capabilities of the TPPs allow them to perform in parallel a number of tasks, both during and outside of data acquisition, which are outlined. The management and control of such a large number of intelligent devices is presented. The discussion covers the hardware configuration of the TPPs; the software running the TPPs; their management, status, and control; exception handling and message logging; and the TPP monitoring tasks. >
A Portable Readout System for Microstrip Silicon Sensors (ALIBAVA)
2009
A readout system for microstrip silicon sensors has been developed. This system is able to measure the collected charge in one or two microstrip silicon sensors by reading out all the channels of the sensor(s), up to 256. The system can operate either with non-irradiated and irradiated sensors as well as with n-type and p-type microstrip silicon sensors. Heavily irradiated sensors will be used at the Super Large Hadron Collider, so this system can be used to research the performance of microstrip silicon sensors in conditions as similar as possible to the Super Large Hadron Collider operating conditions. The system has two main parts: a hardware part and a software part. The hardware part a…
Generation of Hardware/Software systems based on CAL dataflow description
2011
International audience; This paper presents a new development of rapid prototyping tools for system design based on data-flow specifications. In this context, the efficiency of tools for the automatic translation from the data-flow programs to C and/or HDL are assessed by means of two design cases. The paper also introduces the new concept of the automatic synthesis of interfaces. Such generic interfaces are implemented by using an embedded microprocessor, which can support a large variety of interfaces already available as native IP libraries in the case of FPGA. The two design cases described here have been developed, tested and validated on different implementation platforms. The results…
Wide bandwidth impedance meter using low rate random sampling
2008
A novel impedance measurement method based on random sampling of voltage and current signals is proposed. This technique dramatically reduces the sampling frequency requirements, thus circumventing the limitations imposed by maximum speed of the analog to digital converter and the signal processing unit. The lowering of the sampling frequencies allows the design and the implementation of an almost all digital architecture by using a simple microprocessor based embedded system and a digital frequency synthesizer. The basic principles are presented, and the implemented algorithms are described. Experimental results show the instrument performances compared to others commercial alternatives.
MICROPROCESSOR-BASED SUBOPTIMAL CONTROL OF CONVERTER-FED HYPO-HYPERSYNCHRONOUS CASCADE DRIVES
1984
This work consists ofi a theoretic and experimental study o£ a possible practical realization oi a micro pro cess or-based control system using a converter-fad hypo-hypersynchronous cascade. drive. Vlrstly, the design o£ a microprocessor-based controller Is carried out considering an approximate mathematical model, linear-type, o& the drive -In question, by using optimal control techniques. Several physical constraints, -buck as -input variables constraints, state variables constraints and processing time. o& microprocessor are taken -into account. The approach followed attorn us to obtain a suboptimal, closed-loop control system. In addition, In order to carry out a more accurate study ofa…
The readout system and the trigger algorithm implementation for the UFFO Pathfinder
2012
Since the launch of the SWIFT, Gamma-Ray Bursts (GRBs) science has been much progressed. Especially supporting many measurements of GRB events and sharing them with other telescopes by the Gamma-ray Coordinate Network (GCN) have resulted the richness of GRB events, however, only a few of GRB events have been measured within a minute after the gamma ray signal. This lack of sub-minute data limits the study for the characteristics of the UV-optical light curve of the short-hard type GRB and the fast-rising GRB. Therefore, we have developed the telescope named the Ultra-Fast Flash Observatory (UFFO) Pathfinder, to take the sub-minute data for the early photons from GRB. The UFFO Pathfinder has…