Search results for "Multi-core processor"
showing 10 items of 35 documents
Design methods of multithreaded architectures for multicore microcontrollers
2011
The development of electronic technology today has allowed the implementation of complex architectures, which led to the emergence of multicore processors technology. Multicore architectures are built from superscalar and multithreaded processors. Integrating new technologies in embedded applications requires the development of multicore processors that can be integrated into a smaller area like a classic microcontroller. These processors must manage fewer resources and be able to manage multiple tasks simultaneously. In this paper we present a method of modeling, simulation and evaluation of two multithreaded architectures with limited resources, which could be integrated into embedded sys…
Spectral evolution simulation on leading multi-socket, multicore platforms
2011
Spectral evolution simulations based on the observed Very Long Baseline Interferometry (VLBI) radio-maps are of paramount importance to understand the nature of extragalactic objects in astrophysics. This work analyzes the performance and scaling of a spectral evolution algorithm on three leading multi-socket, multi-core architectures. We evaluate three parallel models with different levels of data-sharing: a sharing approach, a privatizing approach and a hybrid approach. Our experiments show that the data-privatizing model is reasonably efficient on medium scale multi-socket, multi-core systems (up to 48 cores) while regardless algorithmic and scheduling optimizations, sharing approach is …
Multithreaded Peripheral Processor for a Multicore Embedded System
2012
Multithreaded and multicore architectures represent a good solution used for increasing of parallelism degree exploited in modern computing systems and they can reduce the power dissipated in the chip by using low-frequency clock signals. These advantages recommend these parallel architectures for integration in the embedded systems, with restrictions imposed by the relatively small integration area. Particularities of embedded applications require hardware support able to handling in real time the peripheral interrupt requests. The performance of this hardware influences the performance of the entire parallel system. The current trend is to integrate in one microcontroller more processors …
On the potential of NoC virtualization for multicore chips
2008
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multi-core chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as …
The Acts project: track reconstruction software for HL-LHC and beyond
2019
The reconstruction of trajectories of the charged particles in the tracking detectors of high energy physics experiments is one of the most difficult and complex tasks of event reconstruction at particle colliders. As pattern recognition algorithms exhibit combinatorial scaling to high track multiplicities, they become the largest contributor to the CPU consumption within event reconstruction, particularly at current and future hadron colliders such as the LHC, HL-LHC and FCC-hh. Current algorithms provide an extremely high standard of physics and computing performance and have been tested on billions of simulated and recorded data events. However, most algorithms were first written 20 year…
Concept and Development of Modular VLIW Processor Based on FPGA
2010
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance level in embedded system. In VLIW architecture, the effectiveness of these processors depends on the ability of compilers to provide sufficient instruction level parallelism(ILP) in program code. Using advanced compiler technology could take these functions, This paper describes research resu…
Multiple modular very long instruction word processors based on field programmable gate arrays
2007
Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…
Enhancing the Sniper Simulator with Thermal Measurement
2014
This paper presents the enhancement of the Sniper multicore / manycore simulator with thermal measurement possibilities using the HotSpot simulator. We present a plugin that interacts with Sniper to retrieve simulation data (integration areas and power consumptions) and calls HotSpot to compute the corresponding thermal results. The plugin also builds a two dimensional floorplan for the simulated microarchitecture. Furthermore we plan to integrate the simulation methodology presented here into an automatic design space exploration process using the multi-objective optimization tool called FADSE. Keywords—multicore; simulator; power consumption; thermal; HotSpot; Sniper
Multithreaded Translation of Ptolemy II Designs on Multicore Platforms
2008
Ptolemy II is an open source environment for system design and test based on component data flow. This paradigm tries to make parallel systems more deterministic and understandable. In this work we propose a technique to translate designs developed with Ptolemy II, into multithreaded Java implementations on multicore platforms. We have chosen Java mainly because Ptolemy II is implemented in Java and then we get direct code reuse. The counterpart is a certain amount of overhead that we expect to be less relevant as Java runtime environment will evolve. The main goals are to produce efficient parallel simulators and software devices with competitive performance level. We show by means of an e…
VLBI-resolution radio-map algorithms: Performance analysis of different levels of data-sharing on multi-socket, multi-core architectures
2012
a b s t r a c t A broad area in astronomy focuses on simulating extragalactic objects based on Very Long Baseline Interferometry (VLBI) radio-maps. Several algorithms in this scope simulate what would be the observed radio-maps if emitted from a predefined extragalactic object. This work analyzes the performance and scaling of this kind of algorithms on multi-socket, multi-core architectures. In particular, we evaluate a sharing approach, a privatizing approach and a hybrid approach on systems with complex memory hierarchy that includes shared Last Level Cache (LLC). In addition, we investigate which manual processes can be systematized and then automated in future works. The experiments sh…