Search results for "PROGRAM"

Fault Emulation for Dependability Evaluation of VLSI Systems

2008

Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inje…

CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC

2018

Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of …

Optimized FPGA-implementation of quadrature DDS

2003

This paper presents the optimized implementation of high performance quadrature direct digital synthesizers (DDS). Although VLSI designs and optimizations have already been discussed in the literature they may not be successfully translated into an FPGA-based technology. This work examines each phase-to-amplitude mapping technique, such as ROM compression and partitioning techniques and the CORDIC algorithm, and it proposes the most suitable structure for Virtex FPGAs in order to obtain the most efficient implementation in terms of area and throughput.

AER Filtering Using GLIDER: VHDL Cellular Automata Description

2008

Cellular Automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop co…

Genetic parameters for early lamb survival and growth in Scottish Blackface sheep1

2008

The objectives of this study were 1) to estimate the heritability of lamb survival and growth in the Scottish Blackface breed; 2) to examine the relationship between lamb survival and live BW; and 3) to investigate the possibility of using lamb survival in a breeding program for this breed. The data used for the analyses contained information about survival and live BW at different ages on 4,459 animals. The records were collected from 1988 to 2003 in a Scottish Blackface flock. Live BW was recorded every 4 wk from birth to 24 wk. Survival was defined either by perinatal or postnatal mortality (up to weaning at 12 wk), or as cumulative survival to 1, 4, 8, and 12 wk. The pedigree file compr…

Programa Cultura

1995

Egotización pública, obscenidad política

2008

Vietējo pašvaldību problēmas zilo pludmaļu piesārņojošo atkritumu situācijas uzlabošanā

2019

Jūras piesārņojošo atkritumu (JPA) galvenais cēlonis ir cilvēka saimnieciskas vai nesaimnieciskas darbības sekas. Lai mazinātu atkritumu nonākšanu pasaules okeānā, sabiedrības ieradumus, attiecībā uz atkritumiem, ir nepieciešams mainīt uz aprites ekonomikas balstītiem pamaprincipiem. Lai piemērotu efektīvas rīcības JPA samazināšanai, būtiski ir aptvert JPA avotus, cēloņus, ietekmes un tendences nākotnē. Bakalaura darba mērķis ir apzināt pašvaldībām iespējamos JPA rašanās riskus un avotus, iegūtos rezultātus analizēt, lai piemērotu efektīvas rīcības, kas mazina draudus atkritumiem rasties un nonākt jūrās. Lai gan Zilā karoga pašvaldībām jau ir labas vides pārvaldības risinājumi, tomēr kampaņ…

An Embedded Real-Time Lane-Keeper for Automatic Vehicle Driving

2008

Automatic vehicle driving involves several issues, such as the capability to follow the road and keep the right lane, to maintain the distance between vehicles, to regulate vehiclepsilas speed, to find the shortest route to a destination. In this paper a real-time automatic lane-keeper is proposed. The main features of the system are the lane markers location process as well as the computation of the vehiclepsilas steering lock. The above techniques require high elaboration speed to execute, check and complete an operation before a prearranged time. Clearly if system processing exceeds the deadline, the whole operation became meaningless or, in the meantime, the vehicle can reach a critical…

Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade

2020

ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module as the building block of its design. To achieve a high input and output bandwidth and substantial processing power, the Global Common Module will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at…