Search results for "RDW"

Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM

2021

This work examines the FPGA programmable logic platforms applied to minimum losses control of a Permanent Magnet Synchronous Motor (PMSM), which represents a flexible solution for the implementation of an advanced digital control algorithm, given their intrinsic parallel structure and the capability to be directly reprogrammable in the field. In particular, design and validation of a FPGA-based Hardware-In-the-Loop (HIL) simulator is proposed, by investigating about data format, quantization and discretization effects and other issues arising during the experimental validation of a controller prototype, in order to reduce the embedded software development cycle and test control systems. The…

Apnea detection using cardiac rhythm and its hardware implementation

2009

Abstract Sleep apnea is a sleep disorder characterized by pauses in breathing during sleep. Its detection is very important to avoid important disorders in the patients such as daytime fatigue and sleepiness, which might be very dangerous in certain work places. One of the methods to detect apnea is based in the cardiac rhythm, measuring some parameters which indicate the presence of respiration abnormalities. This work describes the used algorithm to detect apnea and its hardware implementation in an FPGA device for real time detection using the electrocardiogram (ECG) signal.

An interface protection system based on an embedded metrology system platform

2021

Abstract The aim of this work is to present an interface protection system (IPS) for Distributed Generators (DG) and Energy Storage Systems (ESS). The new prototype of IPS guarantees standard protection requirements, in terms of both voltage and frequency measurement accuracies and trip times. Moreover, it has the additional functionalities of implementing a communication link between the Distribution System Operator (DSO) and the DG and ESS Inverter. The new IPS is based on a smart meter platform with an integrated power line communication modem. Moreover, it has also an integrated metrology section. Experimental tests will show how this last feature allows a significant reduction of the m…

A distributed-memory MPI parallelization scheme for multi-domain incompressible SPH

2022

A parallel scheme for a multi-domain truly incompressible smoothed particle hydrodynamics (SPH) approach is presented. The proposed method is developed for distributed-memory architectures through the Message Passing Interface (MPI) paradigm as communication between partitions. The proposal aims to overcome one of the main drawbacks of the SPH method, which is the high computational cost with respect to mesh-based methods, by coupling a multi-resolution approach with parallel computing techniques. The multi-domain approach aims to employ different resolutions by subdividing the computational domain into non-overlapping blocks separated by block interfaces. The particles belonging to differe…

An exponential spline interpolation for unequally spaced data points

1982

Splitting the data cache: a survey

2000

Recent cache-memory research has focused on approaches that split the first-level data cache into two independent subcaches. The authors introduce a methodology for helping cache designers devise splitting schemes and survey a representative set of the published cache schemes.

2020

Abstract Challenge is a key motivation for videogame play. But what kind of challenge types videogames include, and which of them players prefer? This article helps to answer the above questions by developing and validating Videogame Challenge Inventory (CHA), a psychometrically sound measurement for investigating players’ challenge preferences in videogames. Based on a review of literature, we developed a 38-item version of CHA that was included in a social media user survey (N = 813). An exploratory factor analysis (EFA) revealed a latent structure of five challenge types: Physical, Analytical, Socioemotional, Insight, and Foresight. CHA was amended in another EFA with USA-based survey da…

Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA

2005

This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost, spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained, based on four partial configurations of arithmetic decoder…

Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs

2002

FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA 's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy, we realized an AT40K40 based board ARDOISE.

PyCellBase

2019

Python package for easy retrieval of biological data from heterogeneous sources.