Search results for "RDW"
showing 10 items of 1401 documents
Hardware implementation of real-time Extreme Learning Machine in FPGA: Analysis of precision, resource occupation and performance
2016
Extreme Learning Machine (ELM) on-chip learning is implemented on FPGA.Three hardware architectures are evaluated.Parametrical analysis of accuracy, resource occupation and performance is carried out. Display Omitted Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. Its hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training…
A platform for the development and the validation of HW IP components starting from reference software specifications
2008
Abstract Signal processing algorithms become more and more efficient as a result of the developments of new standards. It is particularly true in the field video compression. However, at each improvement in efficiency and functionality, the complexity of the algorithms is also increasing. Textual specifications, that in the past were the original form of specifications, have been substituted by reference software which became the starting point of any design flow leading to implementation. Therefore, designing an embedded application has become equivalent to port a generic software on a, possibly heterogeneous, embedded platform. Such operation is getting more and more difficult because of …
Sliding Mode Control of Quadratic Boost Converters Based on Min-Type Control Strategy
2023
The paper deals with the control of a quadratic boost converter supplied by low-voltage energy sources, such as photovoltaic panels, fuel cells, or batteries. The control scheme consists of two control loops. A min-type controller governs the inner loop to force the current state of the nominal model to converge in a neighborhood of the equilibrium state. The external loop processes the output tracking error using an integrator, and it allows reconfiguring the converter's working point by changing the equilibrium state given in the input to the internal loop. This configuration assures both zero tracking error of the output voltage and robustness against load and input voltage variations an…
On the Use of GPU for Accelerating Communication-Aware Mapping Techniques
2015
Different communication-aware mapping techniques were proposed in recent years for improving the performance of distributed systems based on both, off-chip and on-chip networks. Some of these proposals were based on heuristic search for finding pseudo-optimal assignments of tasks and processing elements. However, the technology integration improvements have allowed a significant increase in the number of network nodes, requiring the acceleration of the heuristic search. In this paper, we propose a comparative study of the local search method used in a communication-aware mapping technique, when implemented on different parallel architectures. We compare the performance provided by a version…
Generation of nonlinear current-voltage characteristics. A general method
2002
International audience; A general method allowing to construct nonlinear resistors with arbitrary current-voltage (I-V) characteristics is proposed. The example of a cubic I-V characteristic is presented showing a perfect agreement between the theoretical desired resistor and its electronic realization based on analog multipliers.
Parallel Algorithms for Listing Well-Formed Parentheses Strings
1998
We present two cost-optimal parallel algorithms generating the set of all well-formed parentheses strings of length 2n with constant delay for each generated string. In our first algorithm we generate in lexicographic order well-formed parentheses strings represented by bitstrings, and in the second one we use the representation by weight sequences. In both cases the computational model is based on an architecture CREW PRAM, where each processor performs the same algorithm simultaneously on a different set of data. Different processors can access the shared memory at the same time to read different data in the same or different memory locations, but no two processors are allowed to write i…
A novel hardware accelerator for the HEVC intra prediction
2015
International audience; A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 10…
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction
2016
International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…
A comparative analysis of two immersive virtual reality systems in the integration and visualization of natural hand interaction
2022
AbstractIt is generally accepted that the use of natural interaction provides a positive impact in Virtual Reality (VR) applications. Therefore, it is important to understand what is the best way to integrate and visualize this feature in VR. For this reason, this paper presents a comparative study of the integration of natural hand interaction in two immersive VR systems: a Cave Audio Visual Experience (CAVE) system –where users’ real hands are visible– and a non-see-through Head-Mounted Display (HMD) system –where only a virtual representation of the hands is possible–. In order to test the suitability of using this type of interaction in a CAVE and compare it to an HMD, we raise six rese…
Deep Convolutional Neural Network Based Object Detection Inference Acceleration Using FPGA
2022
Object detection is one of the most challenging yet essential computer vision research areas. It means labeling and localizing all known objects of interest on an input image using tightly fit rectangular bounding boxes around the objects. Object detection, having passed through several evolutions and progressions, nowadays relies on the successes of image classification networks based on deep convolutional neural networks. However, as the depth and complication of convolutional neural networks increased, detection speed reduced, and accuracy increased. Unfortunately, most computer vision applications, such as real-time object tracking on an embedded system, requires lightweight, fast and a…