Search results for "RDW"
showing 10 items of 1401 documents
Wireless HROV Control with Compressed Visual Feedback Using Acoustic and RF Links
2020
AbstractUnderwater cooperative robotics offers the possibility to perform challenging intervention applications, such as recovering archeological objects as within the context of the MERBOTS research project, or grasping, transporting and assembly of big objects, using more than one mobile manipulator, as faced by the TWINBOT project. In order to enhance safety during the intervention, it is reasonable to avoid the umbilical, also giving more mobility to the robots, and enabling a broader set of cooperative movements. Several solutions, based on acoustic, radiofrequency (RF) or Visual Light Communication (VLC) have been proposed for underwater communications in the literature. This paper pr…
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
2011
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design
2018
Due to the increase in the number of processing elements in System-on-Chips (SoCs), communication between the cores is becoming complex. A solution to this issue in SoCs gave rise to a new paradigm called Network-on-Chips (NoCs). In NoCs, communication between different cores is achieved using packet based switching techniques. In the deep sub-micron technology, NoCs are more susceptible to different kinds of faults which can be transient, intermittent and permanent. These faults can occur at any component of NoCs. This paper presents a novel Fault-Tolerant Routing (FTR) technique for Mesh-of-Tree (MoT) topology in the presence of router faults. The proposed technique is compared with routi…
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
2018
Increase in the processing elements in a System-on- Chip (SoC) has led to an increasing complexity between the cores in the entire network. This communication bottleneck led to rise in the new paradigm called Network-on-Chip (NoC). These NoC are very much susceptible to various types of faults which can be transient, intermittent or permanent. This paper presents a fault-tolerant routing technique which can route the packets from a source to a destination in presence of permanent faults in the leaf routers of Mesh-of-Tree topology where cores are connected. This is achieved by using reconfiguration in the local ports of the leaf routers by inserting multiplexers as a layer between the leaf …
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
2021
With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures pr…
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
2021
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized …
A TDMA-Based MAC Protocol Supporting Cooperative Communications in Wireless Mesh Networks
2011
This paper proposes a TDMA-based medium access control protocol which enables cooperative communications in multi-hop wireless mesh networks. According to the proposed scheme, each router at the two-hop neighbourhood of each other is allocated to a specific time slot for accommodating either direct or cooperative transmissions in a coordinated manner, controlled by mini-slots which are part of the time slot. Benefiting from the elaborate mini-slot design, channel resources are fairly and efficiently allocated to each router so that no handshake is needed prior to each packet transmission. By providing access priority to cooperative transmission through an optimal relay which is determined b…
A reconfigurable platform for evaluating the performance of QoS networks
2010
Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components. In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. T…
A new Scheme for RPL to handle Mobility in Wireless Sensor Networks
2017
Mobile wireless sensor networks (WSNs) are characterised by dynamic changes in the network topology leading to route breaks and disconnections. The IPv6 routing protocol for low power and lossy networks (RPL), which has become a standard, uses the Trickle timer algorithm to handle changes in the network topology. However, neither RPL nor Trickle timer are well adapted to mobility. This paper investigates the problem of supporting mobility when using RPL. It enhances RPL to fit with sensors' mobility by studying two cases. Firstly, it proposes to modify RPL in order to fit with a dynamic and hybrid topology in the context of medical applications. Secondly, it investigates a more general case…