Search results for "VHDL"
showing 6 items of 26 documents
Modeling and simulation of a digital control design approach for power supply systems
2006
Electronic designers need to model and simulate system features as close as possible to its effective behaviour. Moreover, today, electronics systems are often composed of mixed analog and digital components. The increasing complexity has led to the use of different simulation softwares, each one specific for a particular level of abstraction: mathematical, circuital, behavioural, etc. In order to simulate the entire system these softwares should work together: co-simulation is necessary for digitally controlled power electronics systems. In this paper, the modeling of a digitally controlled switching power supply system using MATLAB/Simulink, ALDEC Active-HDL and Powersys PSIM is presented…
Aprendizaje por Proyectos: Una Aproximación Docente al Diseño Digital Basado en VHDL
2008
Abstract-- Digital design based on hardware description languages is difficult for students, especially when the course covers from basics to advanced design systems and hardware implementation topics. This paper describes the proposal of a course where students have basic knowledge in digital design but null knowledge in hardware description languages as VHDL and FPGA (Field Programmable Gate Array) devices. Using Project Based Learning (PBL), this proposal allows increasing the learning curve, improving motivation and achieving some of the indications given by the European High Education Area (EHEA).
AER Filtering Using GLIDER: VHDL Cellular Automata Description
2008
Cellular Automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop co…
Overview and experimental analysis of MC SPWM techniques for single-phase five level cascaded H-bridge FPGA controller-based
2016
This paper presents an overview and experimental analysis of the MC SPWM techniques for single-phase cascaded H-bridge inverter. The multilevel power converters are an alternative to traditional converters known as “three-level converters”. The voltage waveforms and the related frequency spectra, which have been obtained by simulation analysis in Matlab-Simulink environment, are here reported for all the proposed modulation techniques. The simulation results have been experimentally validated through means of a DC/AC, five-level, single-phase converter prototype with an appropriate test bench.
High Level Modeling and Hardware Implementation of Image Processing Algorithms Using XSG
2019
International audience; Design of Systems-on-Chip has become very common especially with the remarkable advances in the field of high-level system modeling. In recent years, Matlab also offers a Simulink interface for the design of hardware systems. From a high-level specification, Matlab provides self-generation of HDL codes and/or FPGA configuration codes while providing other benefits of easy simulation. In addition, a large part of the Systems-on-Chip use at least one image processing algorithm and at the same time border detection is one of the most used algorithms. This paper presents a study and a hardware implementation of various algorithms of borders detection realized under Xilin…
Reāla laika stereo attēlu korekcija, izmantojot programmējamos loģikas masīvus
2018
Bakalaura darba mērķis ir veikt lēcas radiālo kropļojumu labošanas un attēlu izlīdzināšanas algoritmu izpēti, kā arī veikt to implementāciju programmējamos loģikas masīvos, kā sastāvdaļu no stereo redzes sistēmas, kas paredzēta attēla dziļuma karšu veidošanai. Autors aprakstīs risinājumu algoritmus un, lai demonstrētu Bakalaura darba ietvaros izvirzītās problēmas iespējamo risinājumu, izmantojot programmējamos loģikas masīvus, darba autors veiks praktiskās daļas izstrādi, kas sastāvēs no lēcas radiālo kropļojumu labošanas un attēlu izlīdzināšanas algoritmu implementācijām VHDL valodā. Darbs sastāv no 55 lappusēm, 18 attēliem, 2 tabulām un 7 pielikumiem. Darbā izmantoti 23 literatūras avoti.