Search results for "chip"
showing 10 items of 386 documents
Impact of the erase algorithms on flash memory lifetime
2017
This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance e…
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT
2012
International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…
A fully-digital realtime SoC FPGA based phase noise analyzer with cross-correlation
2017
We report on a fully-digital and realtime operation of a phase noise analyzer using modern digital techniques with cross-correlation. With the advent of system on chip field-programmable gate arrays (SoC FPGAs) embedding hard core central processing unit, coprocessor and FPGA onto a single integrated circuit, the building of sensitive analysis devices for Time & Frequency research is made accessible at virtually no cost and benefits from reconfigurability. Used with high-speed digitizers we have successfully implemented a four-channel system whose preliminary results at 10 MHz shows a residual white noise floor < −185 dBrad2/Hz up to 5 MHz off the carrier, and flicker < −127 dBrad2/Hz using…
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
2019
In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…
Framework for complex quantum state generation and coherent control based on on-chip frequency combs
2018
Integrated frequency combs introduce a scalable framework for the generation and manipulation of complex quantum states (including multi-photon and high-dimensional states), using only standard silicon chip and fiber telecommunications components.
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
2010
The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…
Submarine morphology of the Comoros volcanic archipelago
2021
co-auteur étranger; International audience; A detailed morpho-bathymetric study of the Comoros archipelago, based on mostly unpublished bathymetric data, provides a first glimpse into the submarine section of these islands. It offers a complete view of the distribution of volcanic structures around the archipelago, allowing to discuss the origin and evolution of this volcanism. Numerous volcanic cones and erosional-depositional features have been recognized throughout the archipelago. The magmatic supply is focused below one or several volcanoes for each island, but is also controlled by lithospheric fractures evidenced by volcanic ridges, oriented along the supposed Lwandle-Somali plate bo…
Seasonality and Intensity of Shellfish Harvesting on the North Coast of British Columbia
2013
ABSTRACT Biogeochemical and growth increment analyses show contrasting seasonal patterns of butter clam collection and rates of harvest intensity between archaeological shell midden sites from the Dundas Islands archipelago and the mainland coast in Prince Rupert Harbour, northern British Columbia. Growth increment analysis shows more intensive clam harvest in the Dundas Islands in comparison to the residential sites in Prince Rupert Harbour. Stable oxygen isotope analysis shows multi-seasonal collection of clams in the Dundas Islands and a more seasonally specific emphasis in Prince Rupert Harbour. Comparison of these results to those of similar studies in the Namu region on the central co…
New data about the landscape of the first occupation of Mallorca: Coval Simó (Escorca, Mallorca)
2020
The Coval Simó shelter provides some of the oldest evidence for settlement on the island of Mallorca and the Balearic archipelago. It also has the peculiarity of being a habitat in a mountain area, so that the human groups that settled there had to adapt their agricultural and farming system to this environment. The plant remains (wood charcoal and seeds) recovered in the occupation levels allow us to address these issues, since they are the result of the different activities developed in this cavity: fuel for domestic activities, food for livestock, etc. The results of this study show that between the III and II millennium cal BC, an agricultural system based on livestock and cereal farmi…