Search results for "gate"

The Unbalanced Linguistic Aggregation Operator in Group Decision Making

2012

Published version of an article in the journal: Mathematical problems in engineering. Also available from Hindawi: http://dx.doi.org/10.1155/2012/619162 Many linguistic aggregation methods have been proposed and applied in the linguistic decision- making problems. In practice, experts need to assess a number of values in a side of reference domain higher than in the other one; that is, experts use unbalanced linguistic values to express their evaluation for problems. In this paper, we propose a new linguistic aggregation operator to deal with unbalanced linguistic values in group decision making, we adopt 2-tuple representation model of linguistic values and linguistic hierarchies to expres…

Pneumococcal conjugate vaccine for acute otitis media—yes or no?

2003

Benchmarking plant diversity of Palaearctic grasslands and other open habitats

2021

© 2021 The Authors.

Development of a Fractional PI controller in an FPGA environment for a Robust High-Performance PMSM Electrical Drive

2021

This paper proposes the application of a Fractional Order PI (FOPI) in the speed loop of a high performance PMSM drive to obtain both speed tracking and load rejection performance with a 1-DOF Proportional Integral (PI) controller and 2-DOF Integral Proportional (IP) controller. Hardware validation was implemented in Field Programmable Gate Array on the LabVIEW environment, based on the National Instruments System-on-Module sbRIO-9651 with Xilinx Zynq-7020. Simulation and experimental results are presented to comparing the performance of a PI, IP and FOPI controllers in the speed loop of a Field Oriented Control (FOC) of a Permanent Magnet Synchronous Motor (PMSM).

Fault Emulation for Dependability Evaluation of VLSI Systems

2008

Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inje…

CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC

2018

Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of …

Optimized FPGA-implementation of quadrature DDS

2003

This paper presents the optimized implementation of high performance quadrature direct digital synthesizers (DDS). Although VLSI designs and optimizations have already been discussed in the literature they may not be successfully translated into an FPGA-based technology. This work examines each phase-to-amplitude mapping technique, such as ROM compression and partitioning techniques and the CORDIC algorithm, and it proposes the most suitable structure for Virtex FPGAs in order to obtain the most efficient implementation in terms of area and throughput.

An Embedded Real-Time Lane-Keeper for Automatic Vehicle Driving

2008

Automatic vehicle driving involves several issues, such as the capability to follow the road and keep the right lane, to maintain the distance between vehicles, to regulate vehiclepsilas speed, to find the shortest route to a destination. In this paper a real-time automatic lane-keeper is proposed. The main features of the system are the lane markers location process as well as the computation of the vehiclepsilas steering lock. The above techniques require high elaboration speed to execute, check and complete an operation before a prearranged time. Clearly if system processing exceeds the deadline, the whole operation became meaningless or, in the meantime, the vehicle can reach a critical…

Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade

2020

ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module as the building block of its design. To achieve a high input and output bandwidth and substantial processing power, the Global Common Module will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at…

A Parallel Face Detection System Implemented on FPGA

2007

In this paper, we introduce a methodology for designing a system for face detection and its implementation on FPGA. The chosen face detection method is the well-known convolutional face finder (CFF) algorithm, which consists in a pipeline of convolutions and subsampling operations. Our goal is to define a parallel architecture able to process efficiently this algorithm. We present a dataflow based architecture algorithm adequation (AAA) methodology implemented using the SynDEx software, in order to find the best compromise between the processing power and functionality requirement of each processor element (PE), and the efficiency of algorithm parallelization. We describe a first implementa…