Search results for "hardware"
showing 10 items of 1372 documents
Impact of the erase algorithms on flash memory lifetime
2017
This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance e…
Design and analysis of non-linear circuit with tunnel diode for hybrid control systems
2018
Electric circuits with tunnel diode's represent a classical example of dynamic systems with nonlinearities, which feature piecewise negative damping and multiple equilibria and, as consequence, nontrivial trajectories in the state-space. In this paper, we describe the experimental design and analysis of an electrical circuit, including a tunnel diode, allowing for a storage behavior with bistable output voltage states - low and high. The system is modeled for simulation and an experimental setup is designed and implemented in order to run a formal verification on different tools, applying a variety of hybrid control methods. The nonlinear diode's characteristic curve is experimentally deter…
Experimental investigation on different rainfall energy harvesting structures
2018
In this paper proposes an experimental comparison between different rainfall harvesting devices and the study of the corresponding electrical rectifying circuit. More in detail, three harvesting structures are considered: the cantilever, the bridge and the floating circle. For each of the proposed structure, different waveforms have been acquired and discussed. The processed data have been compared in order to suggest the best choice for the rectifying circuit, from the simplest one to the most endorsed in the technical literature.
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT
2012
International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…
Resistive communications based on neuristors
2017
Memristors are passive elements that allow us to store information using a single element per bit. However, this is not the only utility of the memristor. Considering the physical chemical structure of the element used, the memristor can function at the same time as memory and as a communication unit. This paper presents a new approach to the use of the memristor and develops the concept of resistive communication.
Evolution of application-specific cache mappings
2020
Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processo…
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
2019
In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…
C-switches: Increasing switch radix with current integration scale
2011
In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency, since hop count is also reduced. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we discuss key issues and evaluate an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller single-chip swi…
Electrical Modeling of Monolithically Integrated GMR Based Current Sensors
2018
We report on the electrical compact model, using Verilog-A, of a monolithically integrated giant magnetoresistance (GMR) based electrical current sensors. For this purpose, a specifically designed ASIC (AMS $0.35\mu \mathrm{m}$ technology) has been considered, onto which such sensors have been patterned and fabricated, following a two-steps procedure. This work is focused on the DC regime model extraction, giving evidences of its good performance and stating the bases for subsequent model improvements.
Identification of parameters and harmonic losses of a deep-bar induction motor
2017
High frequency harmonics from a frequency converter causes additional losses in a deep-bar induction motor. The harmonics have their own amplitude and phase with respect to the fundamental signal, but the harmonic loss is only dependent on the amplitude of harmonics. A deep-bar induction motor can be modelled by a triple-cage circuit to take skin effect into account. The triple cage circuit having many parameters could be estimated from a small-signal model of the machine by using Differential Evolution. The correctly estimated parameters make the triple-cage circuit valid in a wide range of frequencies. However, the triple-cage circuit is very complicated which makes it difficult to model …