Search results for "hardware"
showing 10 items of 1372 documents
Fast spiking neural network architecture for low-cost FPGA devices
2012
Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by arti…
Static and dynamic glass transitions in the 10-state Potts glass: What can Monte Carlo simulations contribute?
2002
The p-state Potts glass with infinite range Gaussian interactions can be solved exactly in the thermodynamic limit and exhibits an unconventional phase behavior if p >4: A dynamical transition from ergodic to non-ergodic behavior at a temperature T D is followed by a first order transition at T 0 < T D, where a glass order parameter appears discontinuously, although the latent heat is zero. If one assumes that a similar scenario occurs for the structural glass transition as well (though with the singular behavior at T D rounded off), the p-state Potts glass should be a good test case to develop methods to deal with finite size effects for the static as well as the dynamic transition, and to…
Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC
2019
Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SN…
Magnetic domain-wall racetrack memory for high density and fast data storage
2012
The racetrack memory device is a new concept of Magnetic RAM (MRAM) based on controlling domain wall (DW) motion in ferromagnetic nanowires. It promises ultra-high storage density thanks to the possibility to store multiple narrow DWS per memory cell. By using read and write heads based on magnetic tunnel junctions (MTJ) with perpendicular magnetic anisotropy (PMA) fast data access speed can also be achieved. Thereby the racetrack memory can be used as universal storage to address both embedded and standalone applications. In this paper, we present the device physics, integration circuit and architecture designs of a racetrack memory based on MTJs with PMA. Mixed SPICE simulations at 65 nm …
Lone Star Stack: Architecture of a Disk-Based Archival System
2014
The need for huge storage systems rises with the ever growing creation of data. With growing capacities and shrinking prices, "write once read sometimes" workloads become more common. New data is constantly added, rarely updated or deleted, and every stored byte might be read at any time - a common pattern for digital archives or big data scenarios. We present the Lone Star Stack, a disk based archival storage system building block that is optimized for high reliability and energy efficiency. It provides a POSIX file system interface that uses flash based storage for write-offloading and metadata and the disk-based Lone Star RAID for user data storage. The RAID attempts to spin down disks a…
LoneStar RAID
2016
The need for huge storage archives rises with the ever growing creation of data. With today’s big data and data analytics applications, some of these huge archives become active in the sense that all stored data can be accessed at any time. Running and evolving these archives is a constant tradeoff between performance, capacity, and price. We present the LoneStar RAID, a disk-based storage architecture, which focuses on high reliability, low energy consumption, and cheap reads. It is designed for MAID systems with up to hundreds of disk drives per server and is optimized for “write once, read sometimes” workloads. We use dedicated data and parity disks, and export the data disks as individu…
Importance of the Window Function Choice for the Predictive Modelling of Memristors
2021
Window functions are widely employed in memristor models to restrict the changes of the internal state variables to specified intervals. Here, we show that the actual choice of window function is of significant importance for the predictive modelling of memristors. Using a recently formulated theory of memristor attractors, we demonstrate that whether stable fixed points exist depends on the type of window function used in the model. Our main findings are formulated in terms of two memristor attractor theorems, which apply to broad classes of memristor models. As an example of our findings, we predict the existence of stable fixed points in Biolek window function memristors and their absenc…
Branch-and-cut algorithms for the vehicle routing problem with trailers and transshipments
2013
This article studies the vehicle routing problem with trailers and transshipments VRPTT, a practically relevant, but challenging, generalization of the classical vehicle routing problem. The article makes three contributions: i Building on a nontrivial network representation, two mixed-integer programming formulations for the VRPTT are proposed. ii Based on these formulations, five different branch-and-cut algorithms are developed and implemented. iii The computational behavior of the algorithms is analyzed in an extensive computational study, using a large number of test instances designed to resemble real-world VRPTTs.Copyright © 2013 Wiley Periodicals, Inc. NETWORKS, Vol. 631, 119-133 20…
An Efficient Implementation of Distributed Routing Algorithms for NoCs
2008
The design of NoCs for multi-core chips introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are preferred, heterogeneous blocks, fabrication faults, reliability issues, and chip virtualization may lead to the need of irregular topologies or regions. In this situation, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. LBDR (logic-based distributed routing) is proposed as a new routing method that removes the need of using routing tables at all. LBDR enables the implementation of many routing algorithms on most …
Simulating spin models on GPU
2010
Over the last couple of years it has been realized that the vast computational power of graphics processing units (GPUs) could be harvested for purposes other than the video game industry. This power, which at least nominally exceeds that of current CPUs by large factors, results from the relative simplicity of the GPU architectures as compared to CPUs, combined with a large number of parallel processing units on a single chip. To benefit from this setup for general computing purposes, the problems at hand need to be prepared in a way to profit from the inherent parallelism and hierarchical structure of memory accesses. In this contribution I discuss the performance potential for simulating…