Search results for "hardware"
showing 10 items of 1372 documents
Online Management of Hybrid DRAM-NVMM Memory for HPC
2019
Non-volatile main memories (NVMMs) offer a comparable performance to DRAM, while requiring lower static power consumption and enabling higher densities. NVMM therefore can provide opportunities for improving both energy efficiency and costs of main memory. Previous hybrid main memory management approaches for HPC either do not consider the unique characteristics of NVMMs, depend on high profiling costs, or need source code modifications. In this paper, we investigate HPC applications' behaviors in the presence of NVMM as part of the main memory. By performing a comprehensive study of HPC applications and based on several key observations, we propose an online hybrid memory architecture for …
An Energy Saving Mechanism Based on Vacation Queuing Theory in Data Center Networks
2018
To satisfy the growing need for computing resources, data centers consume a huge amount of power which raises serious concerns regarding the scale of the energy consumption and wastage. One of the important reasons for such energy wastage relates to the redundancies. Redundancies are defined as the backup routing paths and unneeded active ports implemented for the sake of load balancing and fault tolerance. The energy loss may also be caused by the random nature of incoming packets forcing nodes to stay powered on all the times to await for incoming tasks. This paper proposes a re-architecturing of network devices to address energy wastage issue by consolidating the traffic arriving from di…
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips
2019
Use of bus architecture based communication with increasing processing elements in System-on-Chip (SoC) leads to severe degradation of performance and speed of the system. This bottleneck is overcome with the introduction of Network-on-Chips (NoCs). NoCs assist in communication between cores on a single chip using router based packet switching technique. Due to miniaturization, NoCs like every Integrated circuit is prone to different kinds of faults which can be transient, intermittent or permanent. A fault in any one component of such a crucial network can degrade performance leaving other components non-usable. This paper presents a novel Fault-Tolerant routing Algorithm for Mesh-of-Tree …
Silicon dosimeters based on Floating Gate Sensor: design, implementation and characterization
2020
A rad-hard monolithic dosimeter has been implemented and characterized in a standard 180 nm CMOS technology. The radiation sensor (C-sensor) is based on a Floating Gate (FG) MOS discharge principle. The output current is processed by a current-to-voltage (I/V) interface and then converted by a 5-bit flash ADC. The dosimeter is re-usable (FG can be recharged) and can detect a dose up to 1krad (Si) with a resolution of 30rad (Si) typical over temperature 0 to 85°C range. The ADC allows easy further signal processing for calibration and averaging, etc. The power consumption of C-sensor plus I/V interface is < 2mW from a 5 V power supply. The overall layout area is less than 0.25mm2. The Rad…
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
2010
The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…
FOC with Resolver Implementation for PMSM Drives by Using a Low Cost Atmel SAM3X8E Microcontroller
2020
The aim of this paper is the low-cost experimental implementation of a field oriented control strategy for a Permanent Magnet Synchronous Motor (PMSM) by using an Atmel SAM3X8E microcontroller, mounted on an Arduino DUE board. In this electrical drive for PMSM, a resolver is used in order to measure the rotor position and speed: Therefore, the low-cost Arduino DUE performs not only FOC algorithm and phase currents data acquisition, but also a resolver-To-digital converter process, rotor position and speed data acquisition, and resolver signals management. The code has been implemented in the open source Arduino IDE, using C language, whereas the control and plot visualization interfaces hav…
Real-time signal processing in embedded systems
2016
International audience
Run-time scalable NoC for FPGA based virtualized IPs
2017
The integration of virtualized FPGA-based hardware accelerators in a cloud computing is progressing from time to time. As the FPGA has limited resources, the dynamic partial reconfiguration capability of the FPGA is considered to share resources among different virtualized IPs during runtime. On the other hand, the NoC is a promising solution for communication among virtualized FPGA-based IPs. However, not all the virtualized regions of the FPGA will be active all the time. When there is no demand for virtualized IPs, the virtualized regions are loaded with blank bitstreams to save power. However, keeping active the idle components of the NoC connecting with the idle virtualized regions is …
Towards LST split-window algorithm FPGA implementation for CubeSats on-board computations purposes
2019
ABSTRACTNano, pico, and the so-called CubeSat satellites are taking place due to the emergent improvements in both high-performance nano and pico electronics and computational technologies. More th...