Search results for "programma"

showing 10 items of 708 documents

Experimental analysis with FPGA controller-based of MC PWM techniques for three-phase five level cascaded H-bridge for PV applications

2016

The FPGA represents a valid solution for the design of control systems for inverters adopted in the field of PV systems because of their high flexibility of use. This paper presents an experimental analysis of the MC SPWM techniques for a three-phase, five-level, cascaded H-Bridge inverter with FPGA controller-based. Several control algorithms are implemented by means of the VHDL programming language and the output voltage waveforms obtained from the main PWM techniques are compared in terms of THD%. Simulation and experimental results are analysed, compared and discussed.

Engineering020209 energyEnergy Engineering and Power Technology02 engineering and technologySettore ING-IND/32 - Convertitori Macchine E Azionamenti ElettriciGrid connectedControl theoryVHDL0202 electrical engineering electronic engineering information engineeringElectronic engineeringMultilevel power converterRenewable EnergyField-programmable gate arrayFPGAcomputer.programming_languageTotal harmonic distortionSustainability and the EnvironmentRenewable Energy Sustainability and the Environmentbusiness.industry020208 electrical & electronic engineeringH bridgeSettore ING-IND/31 - ElettrotecnicaControl systemInverterVHDLbusinessFPGA; Grid connected; Multilevel power converter; Photovoltaic; VHDL; Energy Engineering and Power Technology; Renewable Energy Sustainability and the EnvironmentPhotovoltaiccomputerPulse-width modulation2016 IEEE International Conference on Renewable Energy Research and Applications (ICRERA)
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Development of the control card for the digitizers of the second generation electronics of AGATA

2012

In this work, the features and development process of the novel control card for the digitizers of AGATA are presented. The board is part of the new hardware proposed for the electronic system of the experiment. In particular, the control card provides the sampling clock for the digitizers, contributes to the synchronization of the digital data and performs the slow control of its associated digitizer cards.

EngineeringControl cardbusiness.industryDigital dataSynchronization (computer science)DetectorProcess (computing)Electrical engineeringAGATAElectronicsbusinessField-programmable gate arrayComputer hardware2012 18th IEEE-NPSS Real Time Conference
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Hardware-in-the-loop implementation for an active heave compensated drawworks

2012

Published version of an article published in the journal: Central European Journal of Engineering. Also available from the publisher at: http://dx.doi.org/10.2478/s13531-011-0062-1 This paper presents the setup and running of a hardware-in-loop (HIL) simulation for an active heave compensated (AHC) draw-works. A simulation model of the draw-works is executed on a PC to simulate the AHC draw-works with a physical PLC. The PLC (ET200S) is configured with a controller architecture that regulates the motor angular displacement and velocity through actuation of the servo valves. Furthermore, a graphical user interface is developed for operation of the AHC system. The HIL test allowed tuning of t…

EngineeringEnvironmental EngineeringDraw-worksController (computing)engineeringdraw-worksactive heave compensation (AHC)Aerospace EngineeringController architectureGeneral Materials Scienceprogrammable logic controller (PLC)Electrical and Electronic EngineeringVDP::Technology: 500::Materials science and engineering: 520SimulationCivil and Structural EngineeringGraphical user interfacebusiness.industryAngular displacementMechanical EngineeringProcess (computing)Hardware-in-the-loop simulationEngineering (General). Civil engineering (General)hardware-in-the-loop (HIL)hoisting rigTA1-2040businessServo
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Latest Frontier Technology and Design of the ATLAS Calorimeter Trigger Board Dedicated to Jet Identification for the LHC Run 3

2016

To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the “A Toroidal LHC ApparatuS” (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which each use different physics objects for the trigger selection. The article focusses on the jet Feature EXtractor (jFEX) prototype, one of the three types of Feature Extractors. Up to 2 TB/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget.…

EngineeringLarge Hadron ColliderCalorimeter (particle physics)010308 nuclear & particles physicsbusiness.industryPhysics::Instrumentation and DetectorsElectrical engineeringLatency (audio)01 natural sciencesSignal030218 nuclear medicine & medical imaging03 medical and health sciences0302 clinical medicineUpgrade0103 physical sciencesMulti-gigabit transceiverSignal integritybusinessField-programmable gate arrayParticle Physics - Experiment
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Commissioning Experience with the ATLAS Level-1 Calorimeter Trigger System

2007

The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects and energy sums. The production of final modules started in 2006, and installation of these modules and the necessary infrastructure…

EngineeringLarge Hadron ColliderIntegration testingbusiness.industryPhysics::Instrumentation and DetectorsReal-time computingATLAS experimentFull scaleCalorimeterData flow diagramNuclear electronicsDetectors and Experimental TechniquesField-programmable gate arraybusiness
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Remote programming of network robots within the UJI Industrial Robotics Telelaboratory: FPGA vision and SNRP network protocol

2009

This paper presents the UJI Industrial Robotics Telelaboratory, which lets Ph.D. and Master’s degree students perform robotics and computer vision tele-experiments. By using this system, students are able to program experiments remotely via the Web, in order to combine the use of a field-programmable gate array (FPGA) to provide real-time vision processing, a conveyor belt, and a Motoman industrial manipulator. This paper introduces the novel SNRP protocol (i.e., Simple Network Robot Protocol), which permits the integration of network robots and sensors within an e-learning platform in a simple and reliable manner. As long as the students are able to interact remotely with a real robotic sc…

EngineeringMachine visionDistributed systemsRobots industrialsRobots IndustrialVisió per ordinador -- Aplicacions industrialsElectrical and Electronic EngineeringProtocol (object-oriented programming)e-learningNetwork architectureTeleroboticsbusiness.industryLocal area networkRoboticsarray (FPGA) visionInternet in educationEnsenyament virtualmultirobot programmingControl and Systems Engineeringhigh-performance field-programmable gateEmbedded systemRobotComputer visioninternetArtificial intelligencebusinessCommunications protocol:Informàtica::Robòtica [Àrees temàtiques de la UPC]industrial robotics telelaboratory
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An FPGA-Based Software Defined Radio Platform for the 2.4GHz ISM Band

2006

A prototype of a Software Defined Radio (SDR) platform has been successfully designed and tested implementing a reconfigurable IEEE 802.11 and ZigBee receiver. The system exploits the reconfiguration capability of an FPGA for implementing a number of receiver configurations that share the same RF front-end. Configurations can be switched at run time, or can share the available logic and radio resource.

EngineeringRF front endRadio receiver designExploitbusiness.industrySoftware radioComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKSFrequency shift keyingControl reconfigurationSoftware-defined radioRemote radio headEmbedded systemField-programmable gate arraybusinessISM bandreceived signal
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Heavy ion SEE test of 2 Gbit DDR3 SDRAM

2011

New generation 2 Gbit DDR3 SDRAMs from Micron, Samsung and Nanya have been tested under heavy ions. SEFIs significantly outweigh random SEU errors even at low LET; however, SEFIs can be mitigated by frequent re-initialization.

EngineeringSingle event upsetGigabitbusiness.industryElectronic engineeringOptoelectronicsHeavy ionbusinessField-programmable gate arrayDDR3 SDRAM2011 12th European Conference on Radiation and Its Effects on Components and Systems
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<title>Architecture for real-time wood inspection</title>

2000

This study has been realized to improve industrial machines that allow to analyze planks by detecting their width and too important defects thanks to a computer vision system. These machines are currently piloted by software with the help of PCs. The aim of our work is to realize a hardware card to increase the processing speed.

EngineeringSoftwarebusiness.industryEmbedded systemSystems architectureImage processingArchitecturebusinessField-programmable gate arrayEdge detectionSPIE Proceedings
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Compact instrumentation for radiation tolerance test of flash memories in space environment

2010

Aim of this work is the description of a test equipment, designed to be integrated on board of a microsatellite, able to investigate the radiation tolerance of non-volatile memory arrays in a real flight experiment. An FPGA-based design was adopted to preserve a high flexibility degree. Besides standard Program/Read/Erase functions, additional features such as failure data screening and latch-up protection have been implemented. The instrument development phase generated, as a by-product, a non-rad-hard version of the instrument that allowed performing in-situ experiments using 60Co and 10 MeV Boron irradiation facilities on Ground. Preliminary measurement results are reported to show the i…

EngineeringTolerance analysisbusiness.industrySystem testingSettore ING-INF/01 - ElettronicaFlash memorySpace equipmentNon-volatile memoryNon-volatile memoryFPGA-based instrumentationRadiation hardneInstrumentation (computer programming)businessField-programmable gate arrayRadiation hardeningInstrumentationComputer hardwareSpace environment
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