Search results for "programma"
showing 10 items of 708 documents
LABCENTER. A remote laboratory system platform
2011
Abstract A web system server especially suited for remote laboratories has been developed. Typical e-learning systems do not offer the possibility to perform a remote laboratory where real experiments can be done online, accessing real hardware located at the University facilities. Allowing students to connect to hardware systems remotely provides them with additional knowledge about real devices; very often, real laboratory devices are time or space restricted. The proposed LABCENTER platform is a general frame designed for remote laboratories connection. The platform is designed to allow an authorized student to connect to hardware systems. As direct hardware systems allow only a single u…
Mācību saturs un kvalitāte bioloģijas mācību priekšmetā pamatskolā
2015
Mācību saturs un kvalitāte bioloģijas mācību priekšmetā pamatskolā. Āboltiņa J., darba vadītājs Dr., prof. Geske, A. Maģistra darbs, 56 lappuses, 19 attēli, 36 literatūras avots, 6 pielikumi. Latviešu valodā. Darba mērķis ir noskaidrot kādas ir bioloģijas mācību satura problēmas pamatskolā un izstrādāt priekšlikumus bioloģijas mācību satura pilnveidei. Veikta teorētiskā literatūras avotu analīze par mācību saturu un tā izveidi. Autore izstrādājusi un veikusi skolotāju aptauju par bioloģijas mācību priekšmeta saturu 9.klasē. Apkopojot visas empīriskajā daļā iegūtās atziņas autore secināja, ka bioloģijas mācību priekšmets 9.klasē ir pārblīvēts un ieteikusi priekšlikumus tā pilnveidei.
Latviešu tautas rakstu izmantošana reklāmā
2019
Bakalaura darbā tiek pētīti jautājumi par kultūrvērtību un datorprogrammām, ar kurām ērtāk un veiksmīgāk veidot jaunus ornamentus un rakstus, izvērtēti pirmie latviešu tautas rakstu un ornamentu pētnieki un viņu devums etnogrāfijas nozarē, veikta aptauja, lai noskaidrotu populārākos un atpazīstamākos latviešu tautas rakstus, noskaidrots, kā latviešu tautas raksti tiek izmantoti reklāmā. Radošais darbs – Bērnu deju ansambļa “Dzīpariņš” 25 gadu jubilejas koncerta afiša, buklets un scenogrāfija. Rezultātā iegūtas atziņas, ka latviešu tautai ir savi tautas raksti, latvju zīmes, kas norāda uz piederību šai valstij, ka vispopulārākās un atpazīstamākās zīmes ir Jumis, Auseklis un Saules zīme, ka l…
Baltijas valstu mazo un vidējo uzņēmumu finanšu atbalsta instrumentu salīdzinājums ar Eiropas Savienības valstu praksi
2017
Bakalaura darbā ir apkopota informācija par sešu Eiropas Savienības valstu nacionālā līmeņa atbalsta programmām maziem un vidējiem uzņēmumiem (MVU). Baltijas valstu (Latvija, Lietuva un Igaunija) programmas ir apskatītas un salīdzinātās ar Eiropas Savienības “vecās” ekonomiskās zonas līdervalstu (Vācija, Francija un Lielbritānija) programmām, lai novērtētu to pielietojamību konkrētās valsts līmenī un atrast labāko un piemērotāko praksi, ko var pielietot Latvijas ekonomikas un tirgus apstākļos. Eiropas Savienības valstīs vidējais MVU procentuālais rādītājs pārsniedz 99% no visu uzņēmumu skaitļa valstīs, kas nosaka tēmas aktualitāti un nepieciešamību analizēt apkārtējo Eiropas Savienības vals…
Wireless versus Wired Network-on-Chip to Enable the Multi- Tenant Multi-FPGAs in Cloud
2021
The new era of computing is not CPU-centric but enriched with all the heterogeneous computing resources including the reconfigurable fabric. In multi-FPGA architecture, either deployed within a data center or as a standalone model, inter-FPGA communication is crucial. Network-on-chip exhibits a promising performance for the integration of one FPGA. A sustainable communication architecture requires stable performance as the number of applications or users grows. Wireless network-on-chip has the potential to be that communication architecture, as it boasts the same performance capability as wired solutions in addition to its multicast capacities. We conducted an exploratory study to investiga…
Feasibility of FPGA accelerated IPsec on cloud
2018
Abstract Hardware acceleration for famous VPN solution, IPsec, has been widely researched already. Still it is not fully covered and the increasing latency, throughput, and feature requirements need further evaluation. We propose an IPsec accelerator architecture in an FPGA and explain the details that need to be considered for a production ready design. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in an SDN network. Related work performance rates in 64 byte packet size for throughput is 1–2 Gbps with 0.2 ms latency in software, and 1–4 Gbps with unknown latencies for hardware solutions. Our proposed architecture is capable to host 1000 concurre…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
Multiple register synchronization with a high-speed serial link using the Aurora protocol
2013
In this work, the development and characterization of a multiple synchronous registers interface communicating with a high-speed serial link and using the Aurora protocol is presented. A detailed description of the developing process and the characterization methods and hardware test benches are also included. This interface will implement the slow control busses of the digitizer cards for the second generation of electronics for the Advanced GAmma Tracking Array (AGATA).
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment
2011
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on th…
The Mu3e Data Acquisition
2020
The Mu3e experiment aims to find or exclude the lepton flavour violating decay $\mu^+\to e^+e^-e^+$ with a sensitivity of one in 10$^{16}$ muon decays. The first phase of the experiment is currently under construction at the Paul Scherrer Institute (PSI, Switzerland), where beams with up to 10$^8$ muons per second are available. The detector will consist of an ultra-thin pixel tracker made from High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), complemented by scintillating tiles and fibres for precise timing measurements. The experiment produces about 100 Gbit/s of zero-suppressed data which are transported to a filter farm using a network of FPGAs and fast optical links. On the filte…