Search results for "programma"
showing 10 items of 708 documents
The MuPix Telescope: A Thin, high Rate Tracking Telescope
2016
The MuPix Telescope is a particle tracking telescope, optimized for tracking low momentum particles and high rates. It is based on the novel High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), designed for the Mu3e tracking detector. The telescope represents a first application of the HV-MAPS technology and also serves as test bed of the Mu3e readout chain. The telescope consists of up to eight layers of the newest prototypes, the MuPix7 sensors, which send data self-triggered via fast serial links to FPGAs, where the data is time-ordered and sent to the PC. A particle hit rate of 1 MHz per layer could be processed. Online tracking is performed with a subset of the incoming data. The ge…
Evaluation of a commercial APD array (Avalanche PhotoDiode) for a readout detector in a hadrontherapy beam characterization application
2010
The aim of the present work is the characterization of the S8898–128–02 Avalanche PhotoDiode array (APDs) from Hamamatsu Photonics. This work includes the implementation of a readout system as well as electronic noise estimation in APDs under several conditions varying integration times and clock frequencies.
A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array
2012
A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/√2) on a single channel is achieved.
Optimal filtering algorithm implementation in FPGAs for the ATLAS TileCal Read-Out drivers
2011
TileCal is the hadronic calorimeter of the ATLAS experiment in the LHC (CERN). Its Read-Out Drivers (RODs) process, in real time, the digitized information coming from the front-end electronics and send it to the Read-Out System. Data processing in the ROD boards is performed in Processing Unit Mezzanine Cards that use commercial DSPs to run the Optimal Filtering (OF) algorithms.
First data with the ATLAS Level-1 Calorimeter Trigger
2008
The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects, and energy sums. The final system consists of over 300 custom-built VME modules, of several different types. The installation at AT…
The Topological Processor for the future ATLAS Level-1 Trigger: From design to commissioning
2014
The ATLAS detector at the Large Hadron Collider (LHC) is designed to measure decay properties of high energetic particles produced in the proton-proton collisions. During its first run, the LHC collided proton bunches at a frequency of 20 MHz, and therefore the detector required a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3×1034cm−2s−1: this represents an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from a physics point of view, a new element will be included in the Level-1 Trigger …
An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger “GOLD”
2012
Abstract: The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the maximum value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the ATLAS Level-1 Calorimeter Trigger electronics chain: the Topological Processor (TP). Such a processor needs fast optical I/O and large aggregate bandwidth to use the information on trigger…
Functional super Read-Out Driver demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter
2011
This work presents the implementation of a functional super Read-Out Driver (sROD) demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) in the LHC experiment. The proposed front-end for the Phase II Upgrade communicates with back-end electronics using a multifiber optical connector with a data rate of 57.6 Gbps using the GBT protocol. This functional sROD demonstrator aims to help in the understanding of the problems that could arise in the upgrade of back-end electronics. The demonstrator is composed of three different boards that have been developed in the framework of ATLAS activities: the Optical Multiplexer Board (OMB), the Read-Out Driver (ROD) and the Optical…
Timing in a FLASH
2017
Abstract A prototype detector, called FLASH (Fast Light Acquiring Start Hodoscope), was built to provide precise Time-of-Flight (TOF) measurements and reference timestamps for detector setups at external beam lines. Radiator bars, made of synthetic fused silica, were coupled to a fast MCP-PMT with 64 channels and read out with custom electronics using Time-over-Threshold (TOT) for signal characterization. The TRB3 system, a high-precision TDC implemented in an FPGA, was used as data acquisition system. The performance of a system consisting of two FLASH units was investigated at a dedicated test experiment at the Mainz Microtron (MAMI) accelerator using its 855 MeV electron beam. The TOT me…
Pre-production validation of the ATLAS level-1 calorimeter trigger system
2006
The Level-1 Calorimeter Trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along …