Search results for "reconfiguration"
showing 10 items of 87 documents
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
2019
In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…
Run-time scalable NoC for FPGA based virtualized IPs
2017
The integration of virtualized FPGA-based hardware accelerators in a cloud computing is progressing from time to time. As the FPGA has limited resources, the dynamic partial reconfiguration capability of the FPGA is considered to share resources among different virtualized IPs during runtime. On the other hand, the NoC is a promising solution for communication among virtualized FPGA-based IPs. However, not all the virtualized regions of the FPGA will be active all the time. When there is no demand for virtualized IPs, the virtualized regions are loaded with blank bitstreams to save power. However, keeping active the idle components of the NoC connecting with the idle virtualized regions is …
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
2019
This paper outlines a multi-application mapping for Mesh-of-Tree (MoT) topology based Network-on-Chip (NoC) design using reconfigurable architecture. A two phase Particle Swarm Optimization (PSO) has been proposed for reconfigurable architecture to minimize the communication cost. In first phase global mapping is done by combining multiple applications and in second phase, reconfiguration is achieved by switching the cores to near by routers using multiplexers. Experimentations have been carried out for several application benchmarks and synthetic applications generated using TGFF tool. The results show significant improvement in terms of communication cost after reconfiguration.
Current fault signatures of Voltage Source Inverters in different reference frames
2016
This paper considers different current patterns used to identify the correct fault signatures in Voltage Source Inverters (VSI). At the beginning, the Authors consider the currents patterns from which a simple or a double fault can be encompassed both in the case of controllable device only or with its free wheeling companion diode. After the discussion of diagnosis algorithm suitable for electrical drives and principally based on a persistent near zero current condition current in the natural phase reference frame, the stationary reference frame is then considered as a tool to identify both the faulted phase as the device or various combination of faulted devices. On the contrary, the Auth…
Designing the 5G network infrastructure: a flexible and reconfigurable architecture based on context and content information
2018
5G networks will have to offer extremely high volumes of content, compared to those of today’s. Moreover, they will have to support heterogeneous traffics, including machine-to-machine, generated by a massive volume of Internet-of-Things devices. Traffic demands will be variable in time and space. In this work, we argue that all this can be achieved in a cost-effective way if the network is flexible and reconfigurable. We present the Flex5Gware network architecture, designed to meet the above requirements. Moreover, we discuss the links between flexibility and reconfigurability, on the one side, and context awareness and content awareness, on the other; we show how two of the building…
An FPGA-Based Adaptive Fuzzy Coprocessor
2005
The architecture of a general purpose fuzzy logic coprocessor and its implementation on an FPGA based System on Chip is described. Thanks to its ability to support a fast dynamic reconfiguration of all its parameters, it is suitable for implementing adaptive fuzzy logic algorithms, or for the execution of different fuzzy algorithms in a time sharing fashion. The high throughput obtained using a pipelined structure and the efficient data organization allows significant increase of the computational capabilities strongly desired in applications with hard real-time constraints.
Radical innovation by theoretical abstraction - a challenge for the user-centred designer
2016
AbstractIt is generally accepted that scientific disciplines such as psychology, sociology, and anthropology contribute beneficially to design by providing understanding of users’ needs, experiences, and desires. Arguably, however, these disciplines have more to contribute, because they include theories and models that can be applied as design frames and principles. More specifically, goal-setting, visualization, thematization, and conceptual reconfiguration are general mechanisms through which theories translate into design contributions. Actualizing radical design solutions via these mechanisms is discussed: theories provide appropriate means of abstraction, which allows ‘distance’ from u…
Shuttling-Based Trapped-Ion Quantum Information Processing
2020
Moving trapped-ion qubits in a microstructured array of radiofrequency traps offers a route toward realizing scalable quantum processing nodes. Establishing such nodes, providing sufficient functionality to represent a building block for emerging quantum technologies, e.g., a quantum computer or quantum repeater, remains a formidable technological challenge. In this review, the authors present a holistic view on such an architecture, including the relevant components, their characterization, and their impact on the overall system performance. The authors present a hardware architecture based on a uniform linear segmented multilayer trap, controlled by a custom-made fast multichannel arbitra…
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
Real Time Image Rotation Using Dynamic Reconfiguration
2002
Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and perfo…