Search results for "vhdl"
showing 10 items of 26 documents
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
2015
This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…
Concept and Development of Modular VLIW Processor Based on FPGA
2010
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance level in embedded system. In VLIW architecture, the effectiveness of these processors depends on the ability of compilers to provide sufficient instruction level parallelism(ILP) in program code. Using advanced compiler technology could take these functions, This paper describes research resu…
Multiple modular very long instruction word processors based on field programmable gate arrays
2007
Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…
Flexible VLIW processor based on FPGA for real-time image processing
2011
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the developm…
Simulation and experimental validation of multicarrier PWM techniques for three-phase five-level cascaded H-bridge with FPGA controller
2017
The FPGA represents a valid solution for the design and implementation of control systems for inverters adopted in many fields of power electronics because of its high flexibility of use. This paper presents an overview and an experimental validation of the MC SPWM techniques for a three-phase, five-level, cascaded H-Bridge inverter with FPGA controller-based. Several control algorithms are here implemented by means of the VHDL programming language and the output voltage waveforms obtained from the main PWM techniques are compared in terms of THD%. Simulation and experimental results are analyzed, compared and discussed.
The Topological Processor for the future ATLAS Level-1 Trigger: From design to commissioning
2014
The ATLAS detector at the Large Hadron Collider (LHC) is designed to measure decay properties of high energetic particles produced in the proton-proton collisions. During its first run, the LHC collided proton bunches at a frequency of 20 MHz, and therefore the detector required a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3×1034cm−2s−1: this represents an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from a physics point of view, a new element will be included in the Level-1 Trigger …
Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal
2014
International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Fe…
A New Model for Sigma-Delta Modulator Oriented to Digitally Controlled DC/DC Converter
2007
Recent research activities have shown the feasibility and advantages of using digital controller ICs specifically developed for high-frequency switching converters, highlighting a challenging future trend in Switched-mode power supplies (SMPS) applications. Up to a few years ago, the application of digital control for SMPS was impractical due to the high cost and low performance of DSP and microcontroller systems, even if the advantages that digital controllers offer were well known, such as immunity to analog component variations and ability to implement sophisticated control schemes and system diagnostics. Digital controller ICs potentially offer other advantages from the integrated desig…
FPGA implementation of Spiking Neural Networks supported by a Software Design Environment
2011
Abstract This paper is focused on the creation of Spiking Neural Networks (SNN) in hardware due to their advantages for certain problem solving and their similarity to biological neural system. One of the main uses of this neural structure is pattern classification. The chosen model for the spiking neuron is the Spike Response Model (SRM). For SNN design and implementation, a software application has been developed to provide easy creation, simulation and automatic generation of the hardware model. VHDL was used for the hardware model. This paper describes the functionality of SNN and the design procedure followed to obtain a working neural system in both software and hardware. Designed VHD…
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques
2004
Modern processors tend to increase the number of registers, being part of them not accessible by the instruction set. Traditionally, the effect of faults in these hidden registers has not been considered during system validation using fault injection. In this paper, a study of the importance of faults in hidden registers is performed. Firstly, we have analysed the sensitivity of hidden registers to faults in combinational logic. In a second phase, we have analysed the impact of the faults occurred in hidden registers on system behaviour. A broad set of permanent and transient faults have been injected into the models of two typical commercial microcontrollers, using a VHDL-based fault injec…