0000000000008955
AUTHOR
Taras Iakymchuk
Live demonstration: multiplexing AER asynchronous channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
Event-based encoding from digital magnetic compass and ultrasonic distance sensor for navigation in mobile systems
Event-based encoding reduces the amount of generated data while keeping relevant information in the measured magnitude. While this encoding is mostly associated with spiking neuromorphic systems, it can be used in a broad spectrum of tasks. The extension of event-based data representation to other sensors would provide advantages related to bandwidth reduction, lower computing requirements, increased processing speed and data processing. This work describes two event-based encoding procedures (magnitude-event and rate-event) for two sensors widely used in industry, especially for navigation in mobile systems: digital magnetic compass and ultrasonic distance sensor. Encoded data meet Address…
Hardware-efficient matrix inversion algorithm for complex adaptive systems
This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively s…
Movement Detection with Event-Based Cameras: Comparison with Frame-Based Cameras in Robot Object Tracking Using Powerlink Communication
Event-based cameras are not common in industrial applications despite the fact that they can add multiple advantages for applications with moving objects. In comparison with frame-based cameras, the amount of generated data is very low while keeping the main information in the scene. For an industrial environment with interconnected systems, data reduction becomes very important to avoid network congestion and provide faster response time. However, the use of new sensors as event-based cameras is not common since they do not usually provide connectivity to industrial buses. This work develops a network node based on a Field Programmable Gate Array (FPGA), including data acquisition and trac…
Brain Activity Characterization Induced by Alcoholic Addiction: Spectral and Causality Analysis of Brain Areas Related to Control and Reinforcement of Impulsivity
Addiction to drugs generates modifications in the brain structure and its functions. In this work, an experimental model is described, using rats to characterize the brain activity induced by alcohol addiction. Four records were obtained using electrodes located in brain areas related to impulsivity control and reinforcement, i.e. the prelimbic (PL) and infralimbic (IL) cortex, together with the hippocampus (HPC). In the records, three main events related to the drinking action were selected: in the previous minute (T1), the first minute while drinking (T2) and the first minute after stopping drinking (T3).
Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials
Material resistance is important since different physicochemical properties can be extracted from it. This work describes a novel resistance measurement method valid for a wide range of resistance values up to 100 GΩ at a low powered, small sized, digitally controlled and wireless communicated device. The analog and digital circuits of the design are described, analysing the main error sources affecting the accuracy. Accuracy and extended uncertainty are obtained for a pattern decade box, showing a maximum of 1 % accuracy for temperatures below 30 ∘ C in the range from 1 MΩ to 100 GΩ. Thermal analysis showed stability up to 50 ∘ C for values below 10 GΩ and systematic deviations for higher …
Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices
With growing demands in real-time control, classification or prediction, algorithms become more complex while low power and small size devices are required. Matrix multiplication (direct or transpose) is common for such computation algorithms. In numerous algorithms, it is also required to perform matrix multiplication repeatedly, where the result of a multiplication is further multiplied again. This work describes a versatile computation procedure and architecture: one of the matrices is stored in internal memory in its circulant form, then, a sequence of direct or transpose multiplications can be performed without timing penalty. The architecture proposes a RAM-ALU block for each matrix c…
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems
Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
Hardware-accelerated spike train generation for neuromorphic image and video processing
Recent studies concerning Spiking Neural Networks show that they are a powerful tool for multiple applications as pattern recognition, image tracking, and detection tasks. The basic functional properties of SNN reside in the use of spike information encoding as the neurons are specifically designed and trained using spike trains. We present a novel and efficient frequency encoding algorithm with Gabor-like receptive fields using probabilistic methods and targeted to FPGA for online pro-cessing. The proposed encoding is versatile, modular and, when applied to images, it is able to perform simple image transforms as edge detection, spot detection or removal, and Gabor-like filtering without a…
Frequency spike encoding using Gabor-like receptive fields
Abstract Spiking Neural Networks (SNN) are a popular field of study. For a proper development of SNN algorithms and applications, special encoding methods are required. Signal encoding is the first step since signals need to be converted into spike trains as the primary input to an SNN. We present an efficient frequency encoding system using receptive fields. The proposed encoding is versatile and it can provide simple image transforms like edge detection, spot detection or removal, or Gabor-like filtering. The proposed encoding can be used in many application areas as image processing and signal processing for detection and classification.
Spiking Neural Networks models targeted for implementation on Reconfigurable Hardware
La tesis presentada se centra en la denominada tercera generación de redes neuronales artificiales, las Redes Neuronales Spiking (SNN) también llamadas ‘de espigas’ o ‘de eventos’. Este campo de investigación se convirtió en un tema popular e importante en la última década debido al progreso de la neurociencia computacional. Las Redes Neuronales Spiking, que tienen no sólo la plasticidad espacial sino también temporal, ofrecen una alternativa prometedora a las redes neuronales artificiales clásicas (ANN) y están más cerca de la operación real de las neuronas biológicas ya que la información se codifica y transmite usando múltiples espigas o eventos en forma de trenes de pulsos. Este campo h…
An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface
High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations’ performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication.…
Fast spiking neural network architecture for low-cost FPGA devices
Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by arti…
Simplified spiking neural network architecture and STDP learning algorithm applied to image classification
Spiking neural networks (SNN) have gained popularity in embedded applications such as robotics and computer vision. The main advantages of SNN are the temporal plasticity, ease of use in neural interface circuits and reduced computation complexity. SNN have been successfully used for image classification. They provide a model for the mammalian visual cortex, image segmentation and pattern recognition. Different spiking neuron mathematical models exist, but their computational complexity makes them ill-suited for hardware implementation. In this paper, a novel, simplified and computationally efficient model of spike response model (SRM) neuron with spike-time dependent plasticity (STDP) lear…
High resistance measurement circuit for fiber materials: Application to moisture content estimation
Abstract Measuring very high resistance values is a difficult task since low voltage or currents are present and thus, noise and amplification must be carefully done, especially when low resistance values are required to be measured using the same circuit, too. This work proposes a novel and accurate measurement instrument for a wide range of resistance values oriented to portable applications, i.e. low power and low supply voltage (5 V) for battery operated equipment, with a small circuit design including analog sensing, digital interface (data reading and control) using a microcontroller and external communication. The proposed circuit includes an inverter attenuator with layout and confi…
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems
Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …
Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise
Adaptive filters are used in a wide range of applications such as noise cancellation, system identification, and prediction. One of the main problems for theses filters is the impulsive noise as it generates algorithm unstability. This work shows the development, simulation and hardware implementation of a new algorithm robust to impulsive noise. Hardware implementation becomes essential in many cases where a real time execution, reduced size, or low power system is needed. An efficient hardware architecture is proposed and different optimizations for size and speed are developed: no need for control state machine, reduced computation requirements due to simplifications, etc. Furthermore, t…
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5…