6533b86ffe1ef96bd12cdf2a
RESEARCH PRODUCT
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
A. RosadoBernabe Linares-barrancoTeresa Serrano-gotarredonaAngel Jimenez-fernandezTaras IakymchukAlejandro Linares-barrancoGabriel Jimenez-morenosubject
EmulationHandshakeComputer sciencebusiness.industryAsynchronous communicationEmbedded systemSerial portModular designbusinessField-programmable gate arraydescription
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance. Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01 Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01 Junta de Andalucía TIC-6091 Ministerio de Economía y Competitividad PRI-PIMCHI-2011-0768
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2014-06-01 |