0000000000008988
AUTHOR
L. Perniola
Distribution of the threshold voltage window in nanocrystal memories with Si dots formed by chemical vapor deposition: Effect of partial self-ordering
Non volatile memories based on Si nanocrystals (Si-ncs) offer an important alternative to conventional floating gate devices, for the numerous potential advantages associated with the discrete-trap structures [1]. Isolated Si-ncs can be obtained by chemical vapor deposition (CVD) through a fully compatible CMOS process. So far, the main limitation for scaling the CVD Si-nc memories at sub-90 nm node is related to the expected fluctuation, from bit to bit, in the device threshold voltage (VTH), due to the spread in the sur- face fraction (Rdot) covered with Si dots [2]. The reason is the assumption that the dot position and the relative distance are fully random. It will be shown that the nu…
Multi-bit storage through Si nanocrystals embedded in SiO2
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. © 2004 Elsevier B.V. All rights reserved.
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
Effects of partial self-ordering of Si dots formed by chemical vapor deposition on the threshold voltage window distribution of Si nanocrystal memories
We study the role that the denuded zone around Si nanocrystals obtained by chemical vapor deposition plays on the fluctuations of the dot surface coverage. In fact, the capture mechanism of the silicon adatoms in the proximity of existing dots restricts the number of possible nucleation sites, the final dot size, and the dot position, thus driving the process toward partial self-order. We numerically evaluate the relative dispersion of surface coverage for several gate areas and compare the results to the fully random case. The coverage dispersion is related to the fluctuations from bit to bit of the threshold voltage window (Δ Vth) distribution of nanocrystal memories. The evaluations, com…
Localized charge storage in nanocrystal memories: Feasibility of a multi-bit cell
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cells for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.