0000000000364533
AUTHOR
A. Macchiarella
showing 5 related works from this author
MULTIPLE SCLEROSIS: PHYSICAL ACTIVITY AND WELL-BEING
2017
Multiple sclerosis (MS) is a chronic disease that affects central nervous system (CNS) – coexists in brain, spinal cord and optic nerves. It can process in three different courses: remitting, progressive and progressive-relapsing. Although there is still no cure for MS, effective strategies are available to modify the disease course, reduce number of relapses, rate of progressions and development of new lesions. Nowadays, moderate physical performance is strongly recommended: besides having positive effects on the body, it can have a positive effect on the psychophysical wellbeing. Essentially there are 3 types of training protocols: aerobic (endurance training), strength training (resistan…
Low-Power Design of Delay Interpolating VCO
2008
In this paper, a design methodology for low-power MCML based delay interpolating VCOs is presented. The methodology allows a fast and accurate graphical evaluation of the optimum design. It utilizes two closed form expressions for the upper and lower oscillation frequencies of the VCO. An expression of the tuning range is also derived. The effectiveness of the proposed design methodology has been tested by simulating several VCOs in an IBM 0.13 mum CMOS technology.
Minimum power-delay product design of MCML gates
2008
This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.
Optimum design of two-level MCML gates
2008
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCML) gates. In particular, we describe a design methodology based on the concept of crossing-point current already introduced for the optimum design of single-level MCML gates. This methodology is suited both for automated implementation and graphic estimate of the optimum design. Moreover, it clearly shows how some important design parameters affect the optimum values of delay and power consumption. Several gates were designed in an IBM 130 nm CMOS technology. The results of SPICE simulations, reported here, demonstrate the effectiveness of the proposed design methodology.
A Design Methodology for Low-Power MCML Ring Oscillators
2007
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.