6533b838fe1ef96bd12a3c6a
RESEARCH PRODUCT
Minimum power-delay product design of MCML gates
G. CarusoA. Macchiarellasubject
Power–delay productbusiness.industryComputer scienceTransistorElectrical engineeringHardware_PERFORMANCEANDRELIABILITYCapacitancelaw.inventionLogic synthesislawLogic gateHardware_INTEGRATEDCIRCUITSElectronic engineeringCurrent-mode logicMinificationIBMbusinessHardware_LOGICDESIGNdescription
This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2008-01-01 | 2008 International Conference on Signals and Electronic Systems |