6533b838fe1ef96bd12a52e6
RESEARCH PRODUCT
Optimum design of two-level MCML gates
A. MacchiarellaG. Carusosubject
Engineeringbusiness.industryNoise (signal processing)SpiceLogic synthesisCMOSComputer engineeringLogic gateElectronic engineeringCurrent-mode logicIBMbusinessDesign methodsHardware_LOGICDESIGNdescription
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCML) gates. In particular, we describe a design methodology based on the concept of crossing-point current already introduced for the optimum design of single-level MCML gates. This methodology is suited both for automated implementation and graphic estimate of the optimum design. Moreover, it clearly shows how some important design parameters affect the optimum values of delay and power consumption. Several gates were designed in an IBM 130 nm CMOS technology. The results of SPICE simulations, reported here, demonstrate the effectiveness of the proposed design methodology.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2008-08-01 | 2008 15th IEEE International Conference on Electronics, Circuits and Systems |