0000000001133508
AUTHOR
Atef Dorai
Service Differentiation for NoC-based Multimedia Applications
International audience; As the communication on-chip evolves toward the global multi-service network, various applications with different service requirements have emerged. A key factor is the support services with a guaranteed quality. The differentiated service with double physical channels is seen as the key technology to achieve this goal. It is focused on the control of traffic and recognizing the need for aspects for the management plan achieved by the bandwidth broker. In this paper, a novel QoS architecture for multimedia application over NoC is proposed. The gains in latency and in resource are possible due to the simplicity of the NoC architecture.
A Novel Architecture for Inter-FPGA Traffic Collision Management
International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…
Un algorithme de gestion de collision efficace pour un NoC déployé sur multi-FPGA
International audience; Les plateformes multi-FPGA sont les solutions les plus prometteuses pour l'émulation de MPSoCs (Multi-Processor System-on-Chip) à base de NoC (Network-on-Chip). Le déploiement d'un NoC de grande taille sur une plateforme multi-FPGA nécessite la mise en place d'interfaces pour la communication inter-FPGA. Des goulots d'étranglements apparaissent, ralentissant fortement les performances du système. Dans ce travail, nous proposons un algorithme de gestion de collision permettant de supprimer ces goulots d'étranglement. L'algorithme de gestion de collision est basé sur l'algorithme de backoff utilisé dans les réseaux informatiques. L'architecture proposée est constituée …
Backoff Hardware Architecture for Inter-FPGA Traffic Management
International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…
Mise en œuvre d’une architecture de gestion de collision pour le déploiement efficace d’un NoC sur multi-FPGA
International audience; Le déploiement d’un NoC (Network On Chip) sur plusieurs FPGA nécessite que des routeurs partagent un même lien de communication entre FPGAs, créant des goulots d’étranglement [1]. Dans ce papier, nous proposons une structure de gestion de collision intégrée entre le NoC et le point d’accès du protocole FPGA. Cette structure est basée sur les algorithmes utilisés dans les réseaux informatiques et adaptée aux NoC [2].