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RESEARCH PRODUCT

Hardware implementation of a robust adaptive filter: Two approaches based in High-Level Synthesis design tools

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Abstract Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. Field Programmable Gate Array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementation has been carried out on the Xilinx ISE development system for FPGA prototyping. In order to test the system for functionality and implementation results, a widely used standard system identification problem is implemented. Results are provided in order to test accuracy, performance and logic occupation.