Search results for " hardware"
showing 10 items of 422 documents
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction
2016
International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…
From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine
2020
Neural networks constitute a well-established design method for current and future generations of artificial intelligence. They depends on regressed arithmetic between perceptrons organized in multiple layers to derive a set of weights that can be used for classification or prediction. Over the past few decades, significant progress has been made in low-complexity designs enabled by powerful hardware/software ecosystems. Built on the foundations of finite-state automata and game theory, Tsetlin Machine is increasingly gaining momentum as an emerging artificial intelligence design method. It is fundamentally based on propositional logic based formulation using booleanized input features. Rec…
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
2019
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
A readout unit for high rate applications
2002
The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…
FADaC
2019
Solid state drives (SSDs) implement a log-structured write pattern, where obsolete data remains stored on flash pages until the flash translation layer (FTL) erases them. erase() operations, however, cannot erase a single page, but target entire flash blocks. Since these victim blocks typically store a mix of valid and obsolete pages, FTLs have to copy the valid data to a new block before issuing an erase() operation. This process therefore increases the latencies of concurrent I/Os and reduces the lifetime of flash memory. Data classification schemes identify data pages with similar update frequencies and group them together. FTLs can use this grouping to design garbage collection strategi…
An Analysis of Flash Page Reuse With WOM Codes
2018
Flash memory is prevalent in modern servers and devices. Coupled with the scaling down of flash technology, the popularity of flash memory motivates the search for methods to increase flash reliability and lifetime. Erasures are the dominant cause of flash cell wear, but reducing them is challenging because flash is a write-once medium— memory cells must be erased prior to writing. An approach that has recently received considerable attention relies on write-once memory (WOM) codes, designed to accommodate additional writes on write-once media. However, the techniques proposed for reusing flash pages with WOM codes are limited in their scope. Many focus on the coding theory alone, whereas o…
Improving MLC flash performance and endurance with extended P/E cycles
2015
The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…
The ATLAS Data Acquisition and High Level Trigger system
2016
Journal of Instrumentation 11(06), P06008 (2016). doi:10.1088/1748-0221/11/06/P06008
Development and Study of a Micromegas Pad-Detector for High Rate Applications
2015
In this paper, the design and the performance of two prototype detectors based on Micromegas technology with a pad readout geometry is discussed. In addition, two alternative implementations of a spark-resistent protection layer on top of the readout pads have been tested to optimize the charge-up behavior of the detector under high rates. The prototype detectors consist of 500 pads with a size of 5x4 mm, each connected to one independent readout channel, and cover an active area of 10x10 cm. The design of these prototypes and its associated readout infrastructure was developed in such a way that it can be easily adapted for large-size detector concepts.
ATLAS TileCal Read Out Driver production
2007
The production tests of the 38 ATLAS TileCal Read Out Drivers (RODs) are presented in this paper. The hardware specifications and firmware functionality of the RODs modules, the test-bench and the test procedure to qualify the boards are described. Finally the performance results, the temperature studies and high rate tests are shown and discussed.