Search results for "Field-programmable gate array"
showing 10 items of 175 documents
High resolution Time of Flight determination based on reconfigurable logic devices for future PET/MR systems
2013
Abstract This contribution shows how to perform Time of Flight (TOF) measurements in PET systems using low-cost Field Programmable Gate Array (FPGA) devices with a resolution better of 100 ps. This is achieved with a proper management of the FPGA internal resources and with an extremely careful device calibration process including both temperature and voltage compensation. Preliminary results are reported.
Time of flight measurements based on FPGA and SiPMs for PET–MR
2014
Coincidence time measurements with SiPMs have shown to be suitable for PET/MR systems. The present study is based on 3 x 3 mm(2) SiPMs, LSO crystals and a conditioning signal electronic circuit. A Constant Fraction Discriminator (CFD) is used to digitalize the signals and a TDC FPGA-implemented is employed for fine time measurements. TDC capability allows processing the arrival of multiple events simultaneously, measuring times under 100 ps. The complete set-up for time measurements results on a resolution of 892 +/- 41 ps for a pair of detectors. The details of such implementation are exposed and the trade-offs of each configuration are discussed. (C) 2013 Elsevier By, All rights reserved,
Upgrade of the ATLAS Level-1 trigger with an FPGA based Topological Processor
2013
The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a proton collision at a frequency of 40 MHz, and thus requires a trigger system to efficiently select events down to a manageable event storage rate of about 400Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5$\mu$s. It is primarily composed of the Calori…
High-resolution multichannel Time-to-Digital Converter core implemented in FPGA for ToF measurements in SiPM-PET
2013
In this contribution, Coincidence Resolving Time (CRT) results with the developed multichannel FPGA-TDC are showed as a function of different configurations for both, the sensor bias voltage and the digitizer threshold. The dependence of the CRT with the sensor matrix temperature, the amount of SiPM active area and the crystal type are also analyzed. Preliminary measurements carried out with a crystal array of 2 mm pixel size and 10 mm height have shown time resolutions for the entire 144 SiPM two-detectors ensemble as good as 800 ps.
A compact system for high precision time measurements ( < 14 ps RMS) and integrated data acquisition for a large number of channels
2011
A high precision ( < 14 ps RMS time resolution) and high channel density ( ~ 256 channels) Time to Digital Converter (TDC) module (realized in FPGAs) with integrated DAQ is presented. The data is transported over up to 8 Gigabit-Ethernet or optical links with up to 3 Gb/s. Slow-Control information is transported over the same links. It can be attached directly to the detector, which allows the elimination of long cables and crate systems. The full 256 channel TDCs are expected to use approximately 30 W electrical power. The module size is 20 cm by 23 cm. Power is provided by a galvanically isolated 48 V low noise power supply. AddOn-boards adapt to the special needs of the detector to be re…
Space variant vision and pipelined architecture for time to impact computation
2002
Image analysis is one of the most interesting ways for a mobile vehicle to understand its environment. One of the tasks of an autonomous vehicle is to get accurate information of what it has in front, to avoid collision or find a way to a target. This task requires real-time restrictions depending on the vehicle speed and external object movement. The use of normal cameras, with homogeneous (squared) pixel distribution, for real-time image processing, usually requires high performance computing and high image rates. A different approach makes use of a CMOS space-variant camera that yields a high frame rate with low data bandwidth. The camera also performs the log-polar transform, simplifyin…
An FPGA-based design for real-time Super Resolution Reconstruction
2018
Since several decades, the camera spatial resolution is gradually increasing with the CMOS technology evolution. The image sensors provide more and more pixels, generating new constraints for the suitable optics. As an alternative, promising solutions propose Super Resolution (SR) image reconstruction to extend the image size without modifying the sensor architecture. Convincing state-of art studies demonstrate that these methods could even be implemented in real-time. Nevertheless, artifacts can be observed in highly textured areas of the image. In this paper, we propose a Local Adaptive Spatial Super Resolution (LASSR) method to fix this limitation. A real-time texture analysis is include…
Real-time Sub-pixel Cross Bar Position Metrology
2002
Many measurement application fields need to calculate cross bar intersection locations of horizontal and vertical bars. The system we developed and that we present in this paper is an embedded system that measures cross bar positions with sub-pixel accuracy on 1024×1024 pixel images delivered by a camera at a 50 MHz data rate in real time. This is done using an algorithm that looks for intersection areas and then locally calculates two lines representing horizontal and vertical bars. The two line intersection is considered to be the bar intersection. To achieve real time, we developed a hybrid architecture in which low level processes are implemented into FPGAs and others into DSPs. As a re…
A predictive function optimization algorithm for multi-spectral skin lesion assessment
2015
The newly introduced Kubelka-Munk Genetic Algorithm (KMGA) is a promising technique used in the assessment of skin lesions. Unfortunately, this method is computationally expensive due to its function inverting process. In the work of this paper, we design a Predictive Function Optimization Algorithm in order to improve the efficiency of KMGA by speeding up its convergence rate. Using this approach, a High-Convergence-Rate KMGA (HCR-KMGA) is implemented onto multi-core processors and FPGA devices respectively. Furthermore, the implementations are optimized using parallel computing techniques. Intensive experiments demonstrate that HCR-KMGA can effectively accelerate KMGA method, while improv…
Remote, web-based laboratory for Programmable Logic Devices
2009
Abstract This work proposes a web-based laboratory for remotely testing FPGA programs on an evaluation board. Using a web browser, the user can download a device configuration file (previously generated with the FPGA commercial tool) and test it in a real FPGA board located in a remote laboratory at the University facilities. The user can control inputs and check outputs’ state. This preliminary study tries to evaluate the possibilities that can be offered to the user, and the restrictions that might apply. Additionally, it describes the proposed infrastructure (hardware and software) needed to successfully deal with all the interesting features that a remote lab system for programmable log…