Search results for "Field-programmable gate array"
showing 10 items of 175 documents
Efficient FPGA Implementation of an Adaptive Noise Canceller
2006
A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
Parallelizing Epistasis Detection in GWAS on FPGA and GPU-Accelerated Computing Systems
2015
This is a post-peer-review, pre-copyedit version of an article published in IEEE - ACM Transactions on Computational Biology and Bioinformatics. The final authenticated version is available online at: http://dx.doi.org/10.1109/TCBB.2015.2389958 [Abstract] High-throughput genotyping technologies (such as SNP-arrays) allow the rapid collection of up to a few million genetic markers of an individual. Detecting epistasis (based on 2-SNP interactions) in Genome-Wide Association Studies is an important but time consuming operation since statistical computations have to be performed for each pair of measured markers. Computational methods to detect epistasis therefore suffer from prohibitively lon…
Real Time Image Rotation Using Dynamic Reconfiguration
2002
Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and perfo…
SoC-Based Implementation of the Backpropagation Algorithm for MLP
2008
The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…
Selective Harmonic Elimination in a 5-Level Single Phase Converter with FPGA Based Controller
2018
Multilevel converters are becoming popular in high-power applications such as motor drives, renewable energy systems and distribution systems. Among all modulation techniques, selective harmonic elimination methods offer high quality voltage waveforms with operations at low switching frequency, hence, they are especially suitable for high-power applications. In this paper, a new analytical expression for the SHE problem formulated for a five-level converter is introduced, which is able to calculate the exact value of the switching angles. After a mathematical description of the proposed approach, this manuscript reports simulation and experimental results and analysis showing achievable res…
Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder
2005
This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…
FPGA/LST-SW Encryption Module Implementation for Satellite Remote Sensing Secure Systems
2020
The need for security of data transmitted from satellites to the ground has increased. Therefore, the need for secure onboard systems is in great demand, particularly in satellite remote sensing missions. This paper describes an approach for a secure Field Programmable Gate Arrays (FPGA) implementation of the Land Surface Temperature Split Window (LST-SW) algorithm, with objective to meat real-time requirements, area optimization and achieved higher Throughput goals to be sufficient for a secure remote sensing satellite applications and missions. The system is designed using VHDL (VHSIC Hardware Description Language) in a Highlevel design method. The experimental results demonstrate that th…
Live demonstration: multiplexing AER asynchronous channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
2017
Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs f…
2017
Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …
Exploring FPGA Based Lock-in Techniques for Brain Monitoring Applications
2017
Functional Near Infrared Spectroscopy (fNIRS) systems for e-health applications usually suffer of poor signal detection mainly due to a low end-to-end signal to noise ratio of the electronics chain. Lock-In Amplifiers (LIA) historically represent a powerful technique helping to improve performances in such circumstances. In this work it has been designed and implemented a digital LIA system, based on a Zynq® Field Programmable Gate Array (FPGA), trying to explore if this technique might improve fNIRS system performances. More broadly, FPGA based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and i…