Search results for "Fpg"
showing 10 items of 131 documents
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
2019
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
A Specialized Architecture for Color Image Edge Detection Based on Clifford Algebra
2013
Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to ex…
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment
2006
Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
2015
This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…
An Efficient Hardware implementation of MQ Decoder of JPEG2000
2014
International audience; JPEG2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG2000 standard has not only better not only has better compression ratios, but it also offers some exciting features. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The MQ decoder of the JPEG2000 standard is an important bottleneck for real-time applications. In order to meet the real-time requirement we propose in this paper a novel architecture for a MQ decoder with high throughput which is co…
An Efficient Hardware Architecture for the HEVC Intra Prediction
2014
International audience; A novel intra prediction hardware architecture forthe High Efficiency Video Coding (HEVC) is presented in thispaper in order to reduce the computation complexity within thisstandard and to accelerate the concerned calculations, and thusto process more and more of video frames at high resolutions. Wepropose a new pipelined structure that we called ProcessingElement (PE) to calculate the angular prediction modes, and werepeat it in three paths that our design composed of. And wepresent, in this paper, a dynamic structure to carry out thePlanar mode. This architecture supports all intra predictionmodes for 8x8 and 4x4 prediction unit sizes. The synthesis resultsshow tha…
The Friedreich's Ataxia protein frataxin modulates DNA base excision repair in prokaryotes and mammals
2010
DNA-repair mechanisms enable cells to maintain their genetic information by protecting it from mutations that may cause malignant growth. Recent evidence suggests that specific DNA-repair enzymes contain ISCs (iron–sulfur clusters). The nuclearencoded protein frataxin is essential for the mitochondrial biosynthesis of ISCs. Frataxin deficiency causes a neurodegenerative disorder named Friedreich's ataxia in humans. Various types of cancer occurring at young age are associated with this disease, and hence with frataxin deficiency. Mice carrying a hepatocyte-specific disruption of the frataxin gene develop multiple liver tumours for unresolved reasons. In the present study, we show that frata…
Technics Amélioration for geo-localization in wsn via smart computing and real time application
2022
New technologies exploiting digital information acquisition by radio frequency techniques are now commonly used in various practical fields. They are most often used to measure a variety of physical variables such as temperature, humidity, speed, etc. and are gathered under the name of Wireless Sensor Networks “WSN”. For this variant of applications, the accurate location of connected sensor nodes remains an important issue for researchers and industrial applications. Indeed, existing localization algorithms can be classified into two categories known as « range-based » and « range-free ». Range-based localization systems are characterized by major drawbacks. The first one is the cost of th…
Flexible VLIW processor based on FPGA for real-time image processing
2011
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the developm…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…