Search results for "Gate"
showing 10 items of 1811 documents
Free and conjugated polyamine content in Citrus sinensis Osbeck, cultivar Brasiliano N.L.92, a Navel orange, at different maturation stages
2004
Biogenic amines, synthesized during physiological metabolic processes of all living organisms, are present in food. At low concentrations, polyamines are essential for cell renewal and growth, but they can be detrimental when consumed in high amount through the diet as they could support abnormal cell growth pathologies. The daily human diet contains more putrescine than spermidine or spermine, mostly derived from fruits. In general, orange fruits contain high levels of put, a fact that could limit their utilization in the daily diet besides the benefits contributed by their strong antioxidant properties. There is therefore an increasing interest in finding plant foods with low polyamine co…
BORDERS AND BORDER CROSSING BETWEEN ART WORLDS. Successful attempts and epic failures to enter new domains in recent British art
2016
The paper attempts to answer, whether it is possible for successful artists in one specific sector to access the domain of another artistic field at their free will. In doing so, this contribution analyses the possible existence of borders and gatekeepers between different art worlds. The aim is not just finding or defining boundaries between art fields, but rather understanding, if boundaries can be pierced through, as well as the conditions that might hinder acceptance. Moving from an art theoretical and philosophical perspective, the present paper will discuss the thesis of Pierre Bourdieu, Howard Becker, Berys Gaut and Joseph Margolis on boundary conditions in the arts. Subsequently the…
Le borgate di Palermo
2012
Lo scritto si riferisce a un lavoro svolto sulle borgate palermitane a partire dall'applicazione dell'analisi morfologica, sulla scorta dell'esperienza del Piano Programma sul centro storico.
Visualization of Memory Map Information in Embedded System Design
2018
Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single v…
Overview and experimental analysis of MC SPWM techniques for single-phase five level cascaded H-bridge FPGA controller-based
2016
This paper presents an overview and experimental analysis of the MC SPWM techniques for single-phase cascaded H-bridge inverter. The multilevel power converters are an alternative to traditional converters known as “three-level converters”. The voltage waveforms and the related frequency spectra, which have been obtained by simulation analysis in Matlab-Simulink environment, are here reported for all the proposed modulation techniques. The simulation results have been experimentally validated through means of a DC/AC, five-level, single-phase converter prototype with an appropriate test bench.
CMOS Capacitance-to-Time Converter-Based Interface for Differential Capacitive Sensors
2020
This paper presents pre-layout simulation results on a CMOS implementation of a capacitance-to-time converter-based electronic interface for differential capacitive sensors. Its simple architecture, comprising only three operational amplifiers (OA) and a digital mixer (inverted XOR gate) allows, by properly setting the values of seven biasing resistors, to fit the working range anywhere from few fF to hundreds of pF, giving the output quasi-digital signals (T and PW) in the useful μs-ms range (appropriate for direct interfacing with general purposes microcontrollers). A couple of illustrative examples are provided.
Optimization of a Time-to-Digital Converter and a coincidence map algorithm for TOF-PET applications
2015
This contribution describes the optimization of a multichannel high resolution Time-to-Digital Converter (TDC) in a Field-Programmable Gate Array (FPGA) initially capable of obtaining time resolutions below 100ps for multiple channels. Due to its fast propagation capability it has taken advantage of the FPGA internal carry logic for accurate time measurements. Furthermore, the implementation of the TDC has been performed in different clock regions and tested with different frequencies as well, achieving improvements of up to 50% for a pair of channels. Moreover, since the TDC is potentially going to be used in a trigger system for Positron Emission Tomography (PET), the algorithm for coinci…
A reconfigurable architecture for autonomous visual-navigation
2003
This paper describes the design of a reconfigurable architecture for implementing image processing algorithms. This architecture is a pipeline of small identical processing elements that contain a programmable logic device (FPGA) and double port memories. This processing system has been adapted to accelerate the computation of differential algorithms. The log-polar vision selectively reduces the amount of data to be processed and simplifies several vision algorithms, making possible their implementation using few hard-ware resources. The reconfigurable architecture design has been devoted to implementation, and has been employed in an autonomous platform, which has power consumption, size a…
AES/FPGA Encryption Module Integration for Satellite Remote Sensing Systems: LST-SW case
2020
Satellite remote sensing embedded systems need to be secure to protect data transmission between satellites and the ground station for any threat can affects the hardware of satellite and interception of data, in addition to unauthorized access to satellite system. This research proposes an approach for a secure integration of FPGA Encryption module based on the iterative looping architecture for remote sensing algorithm and especially for the LST-SW algorithm. The target hardware used in this paper is Virtex-5 XC5VLX50T FPGA from Xilinx. Hardware Description Language was used to design the complete system. The analysis of the proposed designed shows that this implementation can achieved a …
High Level Modeling and Hardware Implementation of Image Processing Algorithms Using XSG
2019
International audience; Design of Systems-on-Chip has become very common especially with the remarkable advances in the field of high-level system modeling. In recent years, Matlab also offers a Simulink interface for the design of hardware systems. From a high-level specification, Matlab provides self-generation of HDL codes and/or FPGA configuration codes while providing other benefits of easy simulation. In addition, a large part of the Systems-on-Chip use at least one image processing algorithm and at the same time border detection is one of the most used algorithms. This paper presents a study and a hardware implementation of various algorithms of borders detection realized under Xilin…