Search results for "Hardware architecture"
showing 10 items of 120 documents
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
A Communication-Aware Topological Mapping Technique for NoCs
2008
Networks---on---Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need…
Analysis of Interconnected Earthing Systems of MV/LV Substations in Urban Areas
2008
The paper proposes a study of the fault current distribution in an extended interconnection of earthing systems, belonging to secondary substations, during a single-line-to-earth fault. By applying the analysis methodology defined by the same authors in some previous works, the paper shows how the value of some important geometrical and electrical parameters of a MV network can influence the value of the earth current at the fault location.
Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping
2013
Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, withou…
Theory of Heterogeneous Circuits With Stochastic Memristive Devices
2022
We introduce an approach based on the Chapman-Kolmogorov equation to model heterogeneous stochastic circuits, namely, the circuits combining binary or multi-state stochastic memristive devices and continuum reactive components (capacitors and/or inductors). Such circuits are described in terms of occupation probabilities of memristive states that are functions of reactive variables. As an illustrative example, the series circuit of a binary memristor and capacitor is considered in detail. Some analytical solutions are found. Our work offers a novel analytical/numerical tool for modeling complex stochastic networks, which may find a broad range of applications.
Improving topological mapping on NoCs
2010
Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping technique for regular and irregular NoC platforms and its application for optimizing application specific NoC based on distributed and source routing.
A random-walk benchmark for single-electron circuits
2021
Mesoscopic integrated circuits aim for precise control over elementary quantum systems. However, as fidelities improve, the increasingly rare errors and component crosstalk pose a challenge for validating error models and quantifying accuracy of circuit performance. Here we propose and implement a circuit-level benchmark that models fidelity as a random walk of an error syndrome, detected by an accumulating probe. Additionally, contributions of correlated noise, induced environmentally or by memory, are revealed as limits of achievable fidelity by statistical consistency analysis of the full distribution of error counts. Applying this methodology to a high-fidelity implementation of on-dema…
Modeling and statistical characterization of wideband indoor radio propagation channels
2010
In this paper, we focus on the modeling of wideband single-input single-output (SISO) mobile fading channels for indoor propagation environments. The derived indoor reference channel model is based on a geometrical scattering model, which consists of an infinite number of scatterers uniformly distributed over the two-dimensional (2D) horizontal plane of a rectangular room. We derive analytical expressions for the probability density function (PDF) of the angle of arrival (AOA), the power delay profile (PDP), and the frequency correlation function (FCF). An efficient sum-of-cisoids (SOC) channel simulator will be derived from the proposed non-realizable reference model. It is shown that the …
Numerical Simulation of Thermal Effects in Coupled Optoelectronic Device-circuit Systems
2008
The control of thermal effects becomes more and more important in modern semiconductor circuits like in the simplified CMOS transceiver representation described by U. Feldmann in the above article Numerical simulation of multiscale models for radio frequency circuits in the time domain. The standard approach for modeling integrated circuits is to replace the semiconductor devices by equivalent circuits consisting of basic elements and resulting in so-called compact models. Parasitic thermal effects, however, require a very large number of basic elements and a careful adjustment of the resulting large number of parameters in order to achieve the needed accuracy.
COMPLEXITY, NOISE AND QUANTUM INFORMATION ON ATOM CHIPS
2008
The realization of quantum logic gates with neutral atoms on atom chips is investigated, including realistic features, such as noise and actual experimental setups.