Search results for "Hardware architecture"
showing 10 items of 120 documents
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
2019
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
A Specialized Architecture for Color Image Edge Detection Based on Clifford Algebra
2013
Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to ex…
A readout unit for high rate applications
2002
The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment
2006
Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…
AMCAS: Advanced Methods for the Co-Design of Complex Adaptive Systems
2006
Abstract This work proposes a new approximation to design and program Complex Adaptive Systems (CAS), these systems comprise neural network, intelligent agents, genetic algorithms, support vector machines and artificial intelligence systems in general. Due to the complexity of such systems, it is necessary to build a design environment able to ease the design work, allowing reusability and easy migration to hardware and/or software. Ptolemy II is used as the base system to simulate and evaluate the designs with different Models of Computation so that an optimum decision about the hardware or software implementation platform can be taken.
Pathological voice analysis via digital signal processing
2015
The interest in pathological voice analysis for specific neurological diseases is growing up aiming to offer more Health-care tele monitoring services since new high performing electronic devices are available for the end-user. In this article we show some parameters that can be digitally extracted and analyzed from pathological voices, in order to find a distinctive sign of the Parkinson disease. As a result, we will show a parameter that gives some information about the Parkinson disease characterization, particularly for male patients. We will also discuss about the needed computational cost related to parameters extraction and elaboration, aiming to target a possible tough yet portable …
An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
2012
By 2014 the LHC will collide proton bunches at 14TeV with an increased instantaneous luminosity up to 3·10³⁴cm⁻²s⁻¹. The resulting higher event rate will challenge the existing ATLAS trigger system. A reduction on the trigger rate can be achieved by selecting interesting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing of a new FPGA based module in the Level-1 trigger: the Topological Processor L1Topo. With L1Topo it will be possible for the first time to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of 1Tb/s. The data …
FPGA Implementation Of Diffusive Realization For A Distributed Control Operator
2010
International audience; We focus on the question of real-time computation for optimal distributed filtering or control applicable to MEMS Arrays. We present an algorithm for the realization of a linear operator solution to a functional equation through its application to a Lyapunov operatorial equation associated to the heat equation in one dimension. It is based on the diffusive realization, and turns to be well suited for fined grained parallel computer architecture as Field Programmable Gate Arrays (FPGA). An effective FPGA implementation has been successfully carried out. Here, we report the main implementation steps and the final measured performances.
Lumped parameter approach of nonlinear networks with transistors
1991
In this chapter we study the lumped parameter modelling of a large class of circuits composed of bipolar transistors, junction diodes and passive elements (resistors, capacitors, inductors). All these elements are nonlinear: the semiconductor components are modelled by “large signal” equivalent schemes, the capacitors and inductors have monotone characteristics while the resistors can be included in a multiport which also has a monotone description.
Advanced time-stamped total data acquisition control front-end for MeV ion beam microscopy and proton beam writing
2013
Many ion-matter interactions exhibit [email protected] time dependences such as, fluorophore emission quenching and ion beam induced charge (IBIC). Conventional event-mode MeV ion microbeam data acquisition systems discard the time information. Here we describe a fast time-stamping data acquisition front-end based on the concurrent processing capabilities of a Field Programmable Gate Array (FPGA). The system is intended for MeV ion microscopy and MeV ion beam lithography. The speed of the system (>240,000 events s^-^1 for four analogue to digital converters (ADC)) is limited by the ADC throughput and data handling speed of the host computer.