Search results for "MAb"

showing 10 items of 1716 documents

FPGA/LST-SW Encryption Module Implementation for Satellite Remote Sensing Secure Systems

2020

The need for security of data transmitted from satellites to the ground has increased. Therefore, the need for secure onboard systems is in great demand, particularly in satellite remote sensing missions. This paper describes an approach for a secure Field Programmable Gate Arrays (FPGA) implementation of the Land Surface Temperature Split Window (LST-SW) algorithm, with objective to meat real-time requirements, area optimization and achieved higher Throughput goals to be sufficient for a secure remote sensing satellite applications and missions. The system is designed using VHDL (VHSIC Hardware Description Language) in a Highlevel design method. The experimental results demonstrate that th…

Computer scienceRemote sensing (archaeology)business.industrySatellite remote sensingVHDLClock ratebusinessEncryptionField-programmable gate arraycomputerThroughput (business)Computer hardwarecomputer.programming_language2020 Fourth International Conference On Intelligent Computing in Data Sciences (ICDS)
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Live demonstration: multiplexing AER asynchronous channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems

2017

Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.

Computer scienceSerial communicationGabor filters02 engineering and technologyMultiplexingMultiplexing0202 electrical engineering electronic engineering information engineeringComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMSField-programmable gate arrayComputer Science::Operating SystemsMassively parallelNeuromorphicsReal-time systemsSpiking neural networkQuantitative Biology::Neurons and CognitionArtificial neural networkbusiness.industry020208 electrical & electronic engineeringField programmable gate arraysNeuromorphic engineeringAsynchronous communicationEmbedded systemVoltage controlbusinessComputer hardwareNeural networksHardware_LOGICDESIGN
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On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs f…

2017

Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …

Computer sciencebusiness.industry020208 electrical & electronic engineeringBiomedical EngineeringSignal Processing Computer-AssistedEquipment Design02 engineering and technologyDifferential signalingHandshakingTransmission (telecommunications)Neuromorphic engineeringAsynchronous communicationEmbedded systemVHDL0202 electrical engineering electronic engineering information engineeringVerilog020201 artificial intelligence & image processingNeural Networks ComputerElectrical and Electronic EngineeringField-programmable gate arraybusinesscomputercomputer.programming_language
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Exploring FPGA Based Lock-in Techniques for Brain Monitoring Applications

2017

Functional Near Infrared Spectroscopy (fNIRS) systems for e-health applications usually suffer of poor signal detection mainly due to a low end-to-end signal to noise ratio of the electronics chain. Lock-In Amplifiers (LIA) historically represent a powerful technique helping to improve performances in such circumstances. In this work it has been designed and implemented a digital LIA system, based on a Zynq® Field Programmable Gate Array (FPGA), trying to explore if this technique might improve fNIRS system performances. More broadly, FPGA based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and i…

Computer sciencebusiness.industryNoise (signal processing)Emphasis (telecommunications)Signallaw.inventionMicroprocessorlawelectrical_electronic_engineeringVHDLDetection theorybusinessField-programmable gate arrayDigital filtercomputerComputer hardwarecomputer.programming_language
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Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices

2020

Executing real-time tasks on dynamically reconfigurable FPGAs requires us to solve the challenges of scheduling and placement. In the past, many approaches have been presented to address these challenges. Still, most of them rely on idealized assumptions about the reconfigurability of FPGAs and the capabilities of commercial tool flows. In our work, we aim at solving these problems leveraging a practically useful 2D slot-based FPGA area model. We present optimal approaches for reconfigurable slot creation, hardware task assignment, and placement creation. We quantitatively compare optimal and heuristics algorithms through simulation experiments and show that the heuristics are rather close …

Computer sciencebusiness.industryReconfigurabilitybusinessField-programmable gate arrayGreedy algorithmHeuristicsReconfigurable computingComputer hardwareScheduling (computing)
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The diagnosis and management of gastric cancer: Expert discussion and recommendations from the 12th ESMO/World Congress on Gastrointestinal Cancer, B…

2011

Well-recognized experts in the field of gastric cancer discussed during the 12th European Society Medical Oncology (ESMO)/World Congress Gastrointestinal Cancer (WCGIC) in Barcelona many important and controversial topics on the diagnosis and management of patients with gastric cancer. This article summarizes the recommendations and expert opinion on gastric cancer. It discusses and reflects on the regional differences in the incidence and care of gastric cancer, the definition of gastro-esophageal junction and its implication for treatment strategies and presents the latest recommendations in the staging and treatment of primary and metastatic gastric cancer. Recognition is given to the ne…

Continuous infusionComputer assisted radiotherapyFolic acidFluorodeoxyglucose f 18Gimeracil plus oteracil potassium plus tegafurInfection controlIntensity modulated radiation therapyDocetaxelCancer stagingMetastatic gastric cancerRisk FactorsPrevalenceDrug fatalityOverall survivalNeoplasm MetastasisPriority journalddc:616Conference paperdigestive oral and skin physiologyFolinic acidHematologyPrognosisOxaliplatinNuclear magnetic resonance imagingBevacizumabSurvival RateOncologyCyanocobalaminPractice Guidelines as TopicDrug dose reductionFluorouracilEsophageal adenocarcinomaHumanPositron emission tomographymedicine.medical_specialtyNeutropeniaStomach cancerStomach neoplasmsMEDLINESide effectStomach adenocarcinomaPatient careIrinotecanHelicobacter infectionPrimary tumorEndoscopic echographyAdvanced cancerEndoscopic mucosal resectionComputer assisted tomographyStomach Neoplasms/*diagnosis/pathology/*therapymedicineHumansGenetic Predisposition to DiseaseGastrointestinal cancerPhase 3 clinical trial (topic)Intensive care medicineSurvival ratePlaceboCapecitabineEpirubicinCa 19-9 antigenStomach Neoplasms/diagnosis/pathology/therapyHelicobacter pyloribusiness.industryCancerTrastuzumabCardiovascular riskmedicine.diseaseCancer susceptibilitydigestive system diseasesSurgeryClinical trialMetastasis potentialExpert opinionMeta analysis (topic)Cancer adjuvant therapyCarcinoembryonic antigenLower esophagus sphincterCisplatinCaloric intakebusinessCancer incidenceRegional differencesAnnals of Oncology
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Experimental Investigation on the Performances of a Multilevel Inverter Using a Field Programmable Gate Array-Based Control System

2019

The Field Programmable Gate Array (FPGA) represents a valid solution for the design of control systems for inverters adopted in many industry applications, because of both its high flexibility of use and its high-performance with respect to other types of digital controllers. In this context, this paper presents an experimental investigation on the harmonic content of the voltages produced by a three-phase, five level cascaded H-Bridge Multilevel inverter with an FPGA-based control board, aiming also to evaluate the performance of the FPGA through the implementation of the main common modulation techniques and the comparison between simulation and experimental results. The control algorithm…

Control and Optimizationmultilevel convertersrenewable energiesComputer scienceEnergy Engineering and Power TechnologyMultilevel converterContext (language use)Renewable energieSettore ING-IND/32 - Convertitori Macchine E Azionamenti Elettricilcsh:TechnologyVHDLElectronic engineeringElectrical and Electronic EngineeringField-programmable gate arrayEngineering (miscellaneous)FPGAcomputer.programming_languageTotal harmonic distortionRenewable Energy Sustainability and the Environmentlcsh:TSettore ING-IND/31 - ElettrotecnicaControl systemHarmonicInvertercomputerPulse-width modulationEnergy (miscellaneous)VoltageEnergies
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Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

2018

Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration te…

Control and Optimizationvideo filteringComputer sciencedigital signal processingEnergy Engineering and Power TechnologyDigital signal processing; Dynamic partial reconfiguration; Energy efficiency; Field Programmable Gate Array; Video filtering02 engineering and technologylcsh:Technology0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringField-programmable gate arrayEngineering (miscellaneous)Digital signal processingenergy efficiencyField Programmable Gate Arraybusiness.industryRenewable Energy Sustainability and the Environmentlcsh:Tenergy efficiency; dynamic partial reconfiguration; Field Programmable Gate Array; digital signal processing; video filteringControl reconfiguration020206 networking & telecommunicationsEnergy consumptionReconfigurable computingdynamic partial reconfigurationEmbedded system020201 artificial intelligence & image processingNode (circuits)businessEnergy (signal processing)Efficient energy useEnergy (miscellaneous)Energies
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PLC security and critical infrastructure protection

2013

Programmable Logic Controllers (PLCs) are the most important components embedded in Industrial Control Systems (ICSs). ICSs have achieved highest standards in terms of efficiency and performance. As a result of that, higher portion of infrastructure in industries has been automated for the comfort of human beings. Therefore, protection of such systems is crucial. It is important to investigate the vulnerabilities of ICSs in order to solve the threats and attacks against critical infrastructure to protect human lives and assets. PLC is the basic building block of an ICS. If PLCs are exploited, overall system will be exposed to the threat. Many believed that PLCs are secured devices due to it…

Control system securityEngineeringbusiness.industryProgrammable logic controllerCritical infrastructure protectionIndustrial control systemComputer securitycomputer.software_genreStuxnetCritical infrastructureData Protection Act 1998Isolation (database systems)businesscomputer2013 IEEE 8th International Conference on Industrial and Information Systems
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Area-efficient FPGA-based FFT processor

2003

A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ‘twiddle factors’ sequentially leads to an area saving up to 35% with respect to other cores.

Cooley–Tukey FFT algorithmSplit-radix FFT algorithmComputer sciencebusiness.industryFast Fourier transformPrime-factor FFT algorithmMultiplicationElectrical and Electronic EngineeringCORDICField-programmable gate arraybusinessTwiddle factorComputer hardwareElectronics Letters
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