Search results for "PG"
showing 10 items of 1521 documents
The sROD demonstrator for the ATLAS Tile Calorimeter Upgrade
2012
This work presents the early design of the super Read-Out Driver (sROD) demonstrator board for the Tile Calorimeter Demonstrator project. This project aims to test the new readout electronics architecture for the Phase 2 Upgrade of the ATLAS Tile Calorimeter, replacing the front-end electronics of one complete drawer with the new electronics during the Long Shutdown 2013, in order to evaluate its performance. The sROD demonstrator board will receive and process data from 48 channels. Moreover the sROD demonstrator board will send preprocessed data to the present trigger system, and will transmit trigger control and timing information (TTC) and Detector Control System (DCS) commands to the f…
Compact instrumentation for radiation tolerance test of flash memories in space environment
2010
Aim of this work is the description of a test equipment, designed to be integrated on board of a microsatellite, able to investigate the radiation tolerance of non-volatile memory arrays in a real flight experiment. An FPGA-based design was adopted to preserve a high flexibility degree. Besides standard Program/Read/Erase functions, additional features such as failure data screening and latch-up protection have been implemented. The instrument development phase generated, as a by-product, a non-rad-hard version of the instrument that allowed performing in-situ experiments using 60Co and 10 MeV Boron irradiation facilities on Ground. Preliminary measurement results are reported to show the i…
Design and testing of the high speed signal densely populated ATLAS calorimeter trigger board dedicate to jet identification
2017
Abstract—The ATLAS experiment has planned a major upgrade in view of the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2021. As part of this, the trigger at Level-1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (three in total), which each uses different physics objects for the trigger selection. The contribution focusses on the jet Feature EXtractor (jFEX) prototype. Up to a data volume of 2 TB/s has to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. Such requirements translate …
Narrowband digital filtering with random frequency hopping spread spectrum
2014
International audience; In digital signal filtering, channels with narrow bandwidth need high order digital filter to be selected without introducing modulation errors. If a carrier randomly switches from a channel to another as in military applications, or some civilian communication standards, it is necessary to detect and estimate these jumps before transposing and analyzing signals in the baseband. This paper presents a real time solution to filter narrow band signals with random frequency hopping spread spectrum. The proposed method is based on three steps. Firstly, the detection of Signal Frequency Hopping (SFH) using the Fast Fourier Transform (FFT), an algorithm to estimate the Domi…
Reconfigurable digital instrumentation based on FPGA
2004
A novel application of FPGA to realize digital test equipment is proposed. It takes advantage of the dynamic reconfigurability of FPGAs so easily tailoring custom test functions in the same instrument. This results in high effective, compact and low cost instruments.
Development of an optical link card for the upgrade phase II of TileCal experiment
2010
This work presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment as part of the evaluation of different technologies for the final choice in the next two years. The board is designed as a mezzanine which can work independently or plugged in the Optical Multiplexer Board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gbps and one SFP optical connector for lower speeds and compatibility with existing hardware as the Read Out Driver. All processing is done in a Stratix II GX FPGA. Details are given on the hardware design including signal and …
Hardware implementation of a robust adaptive filter: Two approaches based in High-Level Synthesis design tools
2009
Abstract Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. Field Programmable Gate Array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementati…
FPGA implementation of a fuel cell emulator
2010
Fuel cell based systems are usually tested with the aid of high-cost and complex auxiliary devices. A fuel cell emulator is an attractive solution for preliminary downward system test. The emulator replaces the effective power source saving cost, volume and hydrogen reserve still ensuring high-accuracy of test results. The use of a highperformance fuel cell model is essential for a successful conclusion of the overall design process. Although the proposed emulator is suitable for each fuel cell type and power level, a 10W Proton Exchange Membrane Fuel Cell emulator is designed and tested. An FPGA based controller models the fuel cell steady-state and dynamic behaviour, including temperature…
Exploring FPGA‐Based Lock‐In Techniques for Brain Monitoring Applications
2017
Functional near‐infrared spectroscopy (fNIRS) systems for e‐health applications usually suffer from poor signal detection, mainly due to a low end‐to‐end signal‐to‐noise ratio of the electronics chain. Lock‐in amplifiers (LIA) historically represent a powerful technique helping to improve performance in such circumstances. In this work a digital LIA system, based on a Zynq® field programmable gate array (FPGA) has been designed and implemented, in an attempt to explore if this technique might improve fNIRS system performance. More broadly, FPGA‐based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and its …
Improvement of energy efficiency and quality of street lighting in South Italy as an action of Sustainable Energy Action Plans. The case study of Com…
2015
Abstract Existing street lighting systems, in most of South Italy cities, are often inefficient due to the obsolescence of lamps and luminaires and of ineffective light control systems unable to implement efficient on-off and dimming strategies. Energy efficiency improvement, in street lighting systems, is often one of the key actions to be adopted by Public Administration in their Sustainable Energy Action Plan in the framework of the “Covenant of Majors” activities. As a task of FACTOR 20 project, a set of planning options has been analysed and proposed. Particularly, street lighting efficiency projects have been studied for representative case studies. A detailed survey of the public lig…