Search results for "PGA"

showing 10 items of 244 documents

Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction

2016

International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…

HEVC[ INFO ] Computer Science [cs]Image compressionComputer scienceReal-time processing1080pFPGAs02 engineering and technologyIntra prediction0202 electrical engineering electronic engineering information engineering[INFO]Computer Science [cs]Field-programmable gate arrayVirtexbusiness.industryReconfigurable computing020206 networking & telecommunicationsFrame rateReconfigurable computingHardware and ArchitectureHardware acceleration020201 artificial intelligence & image processingbusinessSoftwareComputer hardwareImage compressionCoding (social sciences)
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A HARDWARE SOLUTION FOR HEVC INTRA PREDICTION LOSSLESS CODING

2015

International audience; The lossless coding mode of the High Efficiency Video Coding (HEVC) main profile that bypasses transform, quantization, and in-loop filters is described. Compared to the HEVC non-lossless coding mode, the HEVC lossless coding mode provides perfect fidelity and an average bit-rate reduction of 3.2%–13.2%. It also significantly outperforms the existing lossless compression solutions, such as JPEG2000 and JPEG-LS for images as well as WinRAR for data archiving. A fully parallel-based solution is presented in this paper in order to reduce processing time and computation complexity resulting from intra prediction. Two higher performance structures are designed to perform …

HEVC[INFO.INFO-TI] Computer Science [cs]/Image Processing [eess.IV][ INFO.INFO-IM ] Computer Science [cs]/Medical Imaginglossless coding[INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV][ INFO.INFO-TI ] Computer Science [cs]/Image Processing[INFO.INFO-IM] Computer Science [cs]/Medical Imaging[INFO.INFO-IM]Computer Science [cs]/Medical Imagingparallel computing 1intra predictionFPGA
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Brief an Garlieb H. Merkel

1797

Ms. 930a, Nr. 6, Bl. 15r-16r Bruiningk, Karl Axel Christer Freiherr von. Brief an Garlieb H. Merkel, Halle, den 3. Oct[ober] 1797 Autora rokraksts / Autograph, vācu val. / Deutsch, [3] lpp. / S. Attēlu numuri / Bildnummern: 930a-006-1 – 930a-006-2-3 Der spätere Verfechter für die Bauernbefreiung in Livland und Reformer landwirtschaftlicher Methoden Karl Alexander Christer von Bruiningk drückt im Alter von 16 Jahren Merkel gegenüber seinen Dank und seine Bewunderung aus. Zum Zeitpunkt des Schreibens befindet sich der Autor im „Königlichen Pädagogium“ in Halle, also einem Teil der Franckeschen Stiftungen. Diese Muster-Bildungsanstalt war einer der Stationen von Bruiningks Bildungsweg, die meh…

Halles pedagoģijas skoladzimtbūšanaPāvils I Romanovs (Krievijas impērijas ķeizars)Franckesche StiftungenGesetzgebung 1807/1808"Latvieši"LiteraturMerķelis Garlībs Helvigs (1769-1850)Bruiningk Ludolf August von (?-1802)zemnieku brīvlaišana„Hamburgische Schrift“ [gemeint die Zeitschrift „Hamburgischer Correspondent“]Halles Frankes fondiBauernbefreiungBruiningk Karl Axel Christer Freiherr (1782-1848)Merkel Garlieb Helvig (1769-1850)literaūra„Die Letten“:HUMANITIES and RELIGION [Research Subject Categories]Apgaismības laikmetsFranzösische RevolutionLeibeigenschaftHallesches PädagogiumKaiser Paul I von RusslandFranču revolūcijaAufklärunglikumdošana 1807/1808
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Deep Convolutional Neural Network Based Object Detection Inference Acceleration Using FPGA

2022

Object detection is one of the most challenging yet essential computer vision research areas. It means labeling and localizing all known objects of interest on an input image using tightly fit rectangular bounding boxes around the objects. Object detection, having passed through several evolutions and progressions, nowadays relies on the successes of image classification networks based on deep convolutional neural networks. However, as the depth and complication of convolutional neural networks increased, detection speed reduced, and accuracy increased. Unfortunately, most computer vision applications, such as real-time object tracking on an embedded system, requires lightweight, fast and a…

Hardware AcceleratorsAccélérateur matérielApprentissage profondObject detection[INFO.INFO-TS] Computer Science [cs]/Signal and Image ProcessingDétection d'objetsDeep learningConvolutional Neural NetworkCnnFpga
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A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

2019

New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…

Hardware architectureFloating pointGeneral Computer ScienceArtificial neural networkComputer scienceClock rateActivation functionGeneral EngineeringSistemes informàticsAutoencoderArquitectura d'ordinadorsComputational scienceneural network accelerationFPGA implementationdeep neural networksMultilayer perceptronFeedforward neural networks - FFNNFeedforward neural networkXarxes neuronals (Informàtica)General Materials Sciencelcsh:Electrical engineering. Electronics. Nuclear engineeringlcsh:TK1-9971systolic hardware architectureIEEE Access
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A Specialized Architecture for Color Image Edge Detection Based on Clifford Algebra

2013

Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to ex…

Hardware architectureMultispectral MR images.Settore ING-INF/05 - Sistemi Di Elaborazione Delle InformazioniColor histogramComputer scienceColor imagebusiness.industryColor image edge detectionComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISIONFPGA prototypingApplication-specific processorColor quantizationEdge detectionConvolutionComputer Science::Hardware ArchitectureComputer Science::Computer Vision and Pattern RecognitionRGB color modelComputer visionArtificial intelligenceClifford algebrabusinessImage gradient
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Communication Interface Generation For HW/SW Architecture In The STARSoC Environment

2006

Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…

Hardware architectureResource-oriented architectureComputer sciencebusiness.industryInterface (computing)Software prototypingcomputer.software_genreSoftware frameworkComputer architectureEmbedded systemComponent-based software engineeringReference architecturebusinesscomputerFPGA prototype2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)
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Instanton Counting, Quantum Geometry and Algebra

2020

The aim of this memoir for "Habilitation \`a Diriger des Recherches" is to present quantum geometric and algebraic aspects of supersymmetric gauge theory, which emerge from non-perturbative nature of the vacuum structure induced by instantons. We start with a brief summary of the equivariant localization of the instanton moduli space, and show how to obtain the instanton partition function and its generalization to quiver gauge theory and supergroup gauge theory in three ways: the equivariant index formula, the contour integral formula, and the combinatorial formula. We then explore the geometric description of $\mathcal{N} = 2$ gauge theory based on Seiberg-Witten geometry together with it…

High Energy Physics - TheoryQuiver gauge theoryThéorie de jauje de carquoisHigh Energy Physics::Lattice[PHYS.MPHY]Physics [physics]/Mathematical Physics [math-ph]FOS: Physical sciencesQuiver W-algebraqq-characterW-algébre de carquoisHigh Energy Physics::TheorySupergroupgauge theory[MATH.MATH-MP]Mathematics [math]/Mathematical Physics [math-ph]InstantonMathematics - Quantum AlgebraFOS: MathematicsQuantum Algebra (math.QA)[MATH.MATH-MP] Mathematics [math]/Mathematical Physics [math-ph]Representation Theory (math.RT)Algébre vertexComputingMilieux_MISCELLANEOUSMathematical PhysicsSeiberg–Witten geometryIntegrable systemqq-caractéreVertex operator algebra[PHYS.HTHE]Physics [physics]/High Energy Physics - Theory [hep-th]High Energy Physics::PhenomenologyMathematical Physics (math-ph)Localization équivarianteGéométrie de Seiberg–WittenHigh Energy Physics - Theory (hep-th)Théoriede jauje de supergroupe[PHYS.HTHE] Physics [physics]/High Energy Physics - Theory [hep-th]Systèmes intégrablesEquivariant localizationMathematics - Representation Theory
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An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems

2015

This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…

IP ReuseComputer scienceIP-XACT02 engineering and technologyDiscrete Controller Synthesis020204 information systemsIP-XACTVHDLPartial Reconfiguration0202 electrical engineering electronic engineering information engineeringCAD[ INFO.INFO-ES ] Computer Science [cs]/Embedded SystemsElectrical and Electronic EngineeringField-programmable gate arrayFPGAcomputer.programming_languagebusiness.industrySystem GenerationControl reconfigurationcomputer.file_formatComputer Graphics and Computer-Aided DesignAutomationUML MARTE020202 computer hardware & architectureComputer Science Applications[INFO.INFO-ES] Computer Science [cs]/Embedded SystemsModel Driven EngineeringEmbedded system[INFO.INFO-ES]Computer Science [cs]/Embedded SystemsExecutableModel-driven architecturebusinesscomputer
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Bibliotēkas izveide pakalpojuma sniedzēja pierakstīšanās funkcionalitātes ar identitātes sniedzēja imitāciju testēšanai

2021

Kvalifikācijas darbā “Bibliotēkas izveide pakalpojuma sniedzēja pierakstīšanās funkcionalitātes ar identitātes sniedzēja imitāciju testēšanai” šī darba autors ir izveidojis testēšanas bibliotēku, ar kuras palīdzību lietotājs var uzģenerēt korektu SAML 2.0 apgalvojumu un atbildi, ko lietotājs var nosūtīt savam izvēlētajam pakalpojuma sniedzējam, lai pierakstītos pakalpojuma sniedzēja produktā. Šī bibliotēka atvieglo automatizēto lietotājsaskarņu testēšanas procesu sekojošos veidos: - Samazina lietotājsaskarņu testa soļu daudzumu (Selenium komandas), kas uzlabo testu stabilitāti; - Noņem testu atkarību no trešo pušu pakalpojumu sniedzējiem; - Atļauj dinamiski mainīt sistēmas lietotāju atribūt…

Identitātes sniedzējsDatorzinātneIDPSAML 2.0 apgalvojumsPakalpojuma sniedzējsSAML 2.0 atbilde
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