Search results for "RDW"
showing 10 items of 1401 documents
Alignment-Free Sequence Comparison over Hadoop for Computational Biology
2015
Sequence comparison i.e., The assessment of how similar two biological sequences are to each other, is a fundamental and routine task in Computational Biology and Bioinformatics. Classically, alignment methods are the de facto standard for such an assessment. In fact, considerable research efforts for the development of efficient algorithms, both on classic and parallel architectures, has been carried out in the past 50 years. Due to the growing amount of sequence data being produced, a new class of methods has emerged: Alignment-free methods. Research in this ares has become very intense in the past few years, stimulated by the advent of Next Generation Sequencing technologies, since those…
Hardware-accelerated spike train generation for neuromorphic image and video processing
2014
Recent studies concerning Spiking Neural Networks show that they are a powerful tool for multiple applications as pattern recognition, image tracking, and detection tasks. The basic functional properties of SNN reside in the use of spike information encoding as the neurons are specifically designed and trained using spike trains. We present a novel and efficient frequency encoding algorithm with Gabor-like receptive fields using probabilistic methods and targeted to FPGA for online pro-cessing. The proposed encoding is versatile, modular and, when applied to images, it is able to perform simple image transforms as edge detection, spot detection or removal, and Gabor-like filtering without a…
FPGA implementation of Spiking Neural Networks
2012
Abstract Spiking Neural Networks (SNN) have optimal characteristics for hardware implementation. They can communicate among neurons using spikes, which in terms of logic resources, means a single bit, reducing the logic occupation in a device. Additionally, SNN are similar in performance compared to other neural Artificial Neural Network (ANN) architectures such as Multilayer Perceptron, and others. SNN are very similar to those found in the biological neural system, having weights and delays as adjustable parameters. This work describes the chosen models for the implemented SNN: Spike Response Model (SRM) and temporal coding is used. FPGA implementation using VHDL language is also describe…
Fast spiking neural network architecture for low-cost FPGA devices
2012
Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by arti…
Static and dynamic glass transitions in the 10-state Potts glass: What can Monte Carlo simulations contribute?
2002
The p-state Potts glass with infinite range Gaussian interactions can be solved exactly in the thermodynamic limit and exhibits an unconventional phase behavior if p >4: A dynamical transition from ergodic to non-ergodic behavior at a temperature T D is followed by a first order transition at T 0 < T D, where a glass order parameter appears discontinuously, although the latent heat is zero. If one assumes that a similar scenario occurs for the structural glass transition as well (though with the singular behavior at T D rounded off), the p-state Potts glass should be a good test case to develop methods to deal with finite size effects for the static as well as the dynamic transition, and to…
Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC
2019
Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SN…
Magnetic domain-wall racetrack memory for high density and fast data storage
2012
The racetrack memory device is a new concept of Magnetic RAM (MRAM) based on controlling domain wall (DW) motion in ferromagnetic nanowires. It promises ultra-high storage density thanks to the possibility to store multiple narrow DWS per memory cell. By using read and write heads based on magnetic tunnel junctions (MTJ) with perpendicular magnetic anisotropy (PMA) fast data access speed can also be achieved. Thereby the racetrack memory can be used as universal storage to address both embedded and standalone applications. In this paper, we present the device physics, integration circuit and architecture designs of a racetrack memory based on MTJs with PMA. Mixed SPICE simulations at 65 nm …
Lone Star Stack: Architecture of a Disk-Based Archival System
2014
The need for huge storage systems rises with the ever growing creation of data. With growing capacities and shrinking prices, "write once read sometimes" workloads become more common. New data is constantly added, rarely updated or deleted, and every stored byte might be read at any time - a common pattern for digital archives or big data scenarios. We present the Lone Star Stack, a disk based archival storage system building block that is optimized for high reliability and energy efficiency. It provides a POSIX file system interface that uses flash based storage for write-offloading and metadata and the disk-based Lone Star RAID for user data storage. The RAID attempts to spin down disks a…
LoneStar RAID
2016
The need for huge storage archives rises with the ever growing creation of data. With today’s big data and data analytics applications, some of these huge archives become active in the sense that all stored data can be accessed at any time. Running and evolving these archives is a constant tradeoff between performance, capacity, and price. We present the LoneStar RAID, a disk-based storage architecture, which focuses on high reliability, low energy consumption, and cheap reads. It is designed for MAID systems with up to hundreds of disk drives per server and is optimized for “write once, read sometimes” workloads. We use dedicated data and parity disks, and export the data disks as individu…
Importance of the Window Function Choice for the Predictive Modelling of Memristors
2021
Window functions are widely employed in memristor models to restrict the changes of the internal state variables to specified intervals. Here, we show that the actual choice of window function is of significant importance for the predictive modelling of memristors. Using a recently formulated theory of memristor attractors, we demonstrate that whether stable fixed points exist depends on the type of window function used in the model. Our main findings are formulated in terms of two memristor attractor theorems, which apply to broad classes of memristor models. As an example of our findings, we predict the existence of stable fixed points in Biolek window function memristors and their absenc…