Search results for "Scale integration"
showing 10 items of 23 documents
The PAPIA system
1991
In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operatio…
Realistic model of compact VLSI FitzHugh–Nagumo oscillators
2013
In this article, we present a compact analogue VLSI implementation of the FitzHugh–Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off freque…
Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems
2006
Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a great promise by enabling those techniques to execute models faster. This paper focuses on how run-time reconfiguration techniques can be used for emulating the occurrence of transient faults in VLSI models. Although the use of FPGAs for that purpose has been restricted so far to the well-known bit-flip fault model, recent studies in fault repres…
Fault Emulation for Dependability Evaluation of VLSI Systems
2008
Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inje…
A VLSI for deskewing and fault tolerance in LVDS links
2005
The device presented at this work is a switch implemented in a 0.35 mum CMOS process for compensating the skew which affects parallel data signal transmissions and for providing fault tolerance in large scale scalable systems, for instance used in trigger farms for high energy physics experiments. The SWIFT chip (SWItch for Fault Tolerance) is part of a cluster built around commercially components which has been inspired by the LHCb experiment. The skew is extremely important because it directly affects the sample window available to the receiver logic and either forces to use quality and expensive cables in order to minimize its effects or reduces the maximum signal transmission range or d…
CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC
2018
Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of …
Visual spike-based convolution processing with a Cellular Automata architecture
2010
this paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based convolution filters inspired by Cellular Automata for AER vision processing. Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. AER is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas an…
Optimized FPGA-implementation of quadrature DDS
2003
This paper presents the optimized implementation of high performance quadrature direct digital synthesizers (DDS). Although VLSI designs and optimizations have already been discussed in the literature they may not be successfully translated into an FPGA-based technology. This work examines each phase-to-amplitude mapping technique, such as ROM compression and partitioning techniques and the CORDIC algorithm, and it proposes the most suitable structure for Virtex FPGAs in order to obtain the most efficient implementation in terms of area and throughput.
AER Filtering Using GLIDER: VHDL Cellular Automata Description
2008
Cellular Automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop co…
Programmable VLSI cubic-like function implementation
2006
An analogue VLSI implementation of a cubic-like function is presented, whose design is focused to reduce the circuit complexity. Simulations show that the V–I characteristic of the circuit resembles a cubic function, which can be easily adjusted by changing the bias parameters.