Search results for "VHDL"
showing 10 items of 26 documents
FPGA/LST-SW Encryption Module Implementation for Satellite Remote Sensing Secure Systems
2020
The need for security of data transmitted from satellites to the ground has increased. Therefore, the need for secure onboard systems is in great demand, particularly in satellite remote sensing missions. This paper describes an approach for a secure Field Programmable Gate Arrays (FPGA) implementation of the Land Surface Temperature Split Window (LST-SW) algorithm, with objective to meat real-time requirements, area optimization and achieved higher Throughput goals to be sufficient for a secure remote sensing satellite applications and missions. The system is designed using VHDL (VHSIC Hardware Description Language) in a Highlevel design method. The experimental results demonstrate that th…
Aprendizaje por Proyectos: Una Aproximación Docente al Diseño Digital Basado en VHDL
2008
Abstract-- Digital design based on hardware description languages is difficult for students, especially when the course covers from basics to advanced design systems and hardware implementation topics. This paper describes the proposal of a course where students have basic knowledge in digital design but null knowledge in hardware description languages as VHDL and FPGA (Field Programmable Gate Array) devices. Using Project Based Learning (PBL), this proposal allows increasing the learning curve, improving motivation and achieving some of the indications given by the European High Education Area (EHEA).
Concept and Development of Modular VLIW Processor Based on FPGA
2010
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance level in embedded system. In VLIW architecture, the effectiveness of these processors depends on the ability of compilers to provide sufficient instruction level parallelism(ILP) in program code. Using advanced compiler technology could take these functions, This paper describes research resu…
Exploring FPGA‐Based Lock‐In Techniques for Brain Monitoring Applications
2017
Functional near‐infrared spectroscopy (fNIRS) systems for e‐health applications usually suffer from poor signal detection, mainly due to a low end‐to‐end signal‐to‐noise ratio of the electronics chain. Lock‐in amplifiers (LIA) historically represent a powerful technique helping to improve performance in such circumstances. In this work a digital LIA system, based on a Zynq® field programmable gate array (FPGA) has been designed and implemented, in an attempt to explore if this technique might improve fNIRS system performance. More broadly, FPGA‐based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and its …
Multiple modular very long instruction word processors based on field programmable gate arrays
2007
Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…
FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches
2011
Adaptive filters are used in a wide range of applications such as echo cancellation, noise cancellation, system identification, and prediction. Its hardware implementation becomes essential in many cases where real-time execution is needed. However, impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms, particularly in specific hardware platforms. Field-programmable gate arrays (FPGAs) are used widely for real-time applications where timing requirements are strict. Nowadays, two main design processes can be followed for embedded system design…
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs f…
2017
Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …
Simulation and experimental validation of multicarrier PWM techniques for three-phase five-level cascaded H-bridge with FPGA controller
2017
The FPGA represents a valid solution for the design and implementation of control systems for inverters adopted in many fields of power electronics because of its high flexibility of use. This paper presents an overview and an experimental validation of the MC SPWM techniques for a three-phase, five-level, cascaded H-Bridge inverter with FPGA controller-based. Several control algorithms are here implemented by means of the VHDL programming language and the output voltage waveforms obtained from the main PWM techniques are compared in terms of THD%. Simulation and experimental results are analyzed, compared and discussed.
Reāla laika stereo attēlu korekcija, izmantojot programmējamos loģikas masīvus
2018
Bakalaura darba mērķis ir veikt lēcas radiālo kropļojumu labošanas un attēlu izlīdzināšanas algoritmu izpēti, kā arī veikt to implementāciju programmējamos loģikas masīvos, kā sastāvdaļu no stereo redzes sistēmas, kas paredzēta attēla dziļuma karšu veidošanai. Autors aprakstīs risinājumu algoritmus un, lai demonstrētu Bakalaura darba ietvaros izvirzītās problēmas iespējamo risinājumu, izmantojot programmējamos loģikas masīvus, darba autors veiks praktiskās daļas izstrādi, kas sastāvēs no lēcas radiālo kropļojumu labošanas un attēlu izlīdzināšanas algoritmu implementācijām VHDL valodā. Darbs sastāv no 55 lappusēm, 18 attēliem, 2 tabulām un 7 pielikumiem. Darbā izmantoti 23 literatūras avoti.
The Topological Processor for the future ATLAS Level-1 Trigger: From design to commissioning
2014
The ATLAS detector at the Large Hadron Collider (LHC) is designed to measure decay properties of high energetic particles produced in the proton-proton collisions. During its first run, the LHC collided proton bunches at a frequency of 20 MHz, and therefore the detector required a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3×1034cm−2s−1: this represents an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from a physics point of view, a new element will be included in the Level-1 Trigger …