Search results for "arithmetic"
showing 10 items of 271 documents
Efficient FPGA Implementation of an Adaptive Noise Canceller
2006
A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
SoC-Based Implementation of the Backpropagation Algorithm for MLP
2008
The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…
The promise of spintronics for unconventional computing
2021
Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/o…
Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder
2005
This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…
Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding
2013
The H.264/AVC video coding standard introduces some improved tools in order to increase compression efficiency. Moreover, the multi-view extension of H.264/AVC, called H.264/MVC, adopts many of them. Among the new features, variable block-size motion estimation is one which contributes to high coding efficiency. Furthermore, it defines a different prediction structure that includes hierarchical bidirectional pictures, outperforming traditional Group of Pictures patterns in both scenarios: single-view and multi-view. However, these video coding techniques have high computational complexity. Several techniques have been proposed in the literature over the last few years which are aimed at acc…
Fields with Discrete Valuations
2019
In the present chapter, before embarking on our arithmetic applications, we recall basic facts on local fields for the convenience of the geometer reader.
Some remarks on unconditionally convergent multipliers
2017
We present some results concerning the representation of unconditionally convergent multipliers, including a reformulation of a conjecture of Balazs and Stoeva.
Pairwise DNA Sequence Alignment Optimization
2015
This chapter presents a parallel implementation of the Smith-Waterman algorithm to accelerate the pairwise alignment of DNA sequences. This algorithm is especially computationally demanding for long DNA sequences. Parallelization approaches are examined in order to deeply explore the inherent parallelism within Intel Xeon Phi coprocessors. This chapter looks at exploiting instruction-level parallelism within 512-bit single instruction multiple data instructions (vectorization) as well as thread-level parallelism over the many cores (multithreading using OpenMP). Between coprocessors, device-level parallelism through the compute power of clusters including Intel Xeon Phi coprocessors using M…
The minimal free resolution of fat almost complete intersections in ℙ1 x ℙ1
2017
AbstractA current research theme is to compare symbolic powers of an ideal I with the regular powers of I. In this paper, we focus on the case where I = IX is an ideal deûning an almost complete intersection (ACI) set of points X in ℙ1 × ℙ1. In particular, we describe a minimal free bigraded resolution of a non-arithmetically Cohen-Macaulay (also non-homogeneous) set 𝒵 of fat points whose support is an ACI, generalizing an earlier result of Cooper et al. for homogeneous sets of triple points. We call 𝒵 a fat ACI.We also show that its symbolic and ordinary powers are equal, i.e, .
A Note on Keys and Keystreams of Chacha20 for Multi-key Channels
2018
In this paper we analyze the keystreams generated by the Chacha20 stream cipher. We also compare these to the ones generated by its predecessor, the RC4 stream cipher. Due to the proposed multi-key channels in the upcoming TLS 1.3 standard we analyze the behavior of the keystream in the boundary case where there is a single bit difference between two keys used for the initiation of the stream cipher algorithms. The goal is to check whether a single bit change in the key has any predictable influence on the bits of the keystream output.