Search results for "chip"

showing 10 items of 386 documents

Data Transmission and Thermo-Optic Tuning Performance of Dielectric-Loaded Plasmonic Structures Hetero-Integrated on a Silicon Chip

2012

We demonstrate experimental evidence of the data capture and the low-energy thermo-optic tuning credentials of dielectric-loaded plasmonic structures integrated on a silicon chip. We show 7-nm thermo-optical tuning of a plasmonic racetrack-resonator with less than 3.3 mW required electrical power and verify error-free 10-Gb/s transmission through a 60-mu m-long dielectric-loaded plasmonic waveguide. We demonstrate experimental evidence of the data capture and the low-energy thermo-optic tuning credentials of dielectric-loaded plasmonic structures integrated on a silicon chip. We show 7-nm thermo-optical tuning of a plasmonic racetrack-resonator with less than 3.3 mW required electrical powe…

EXPRESSIONMaterials scienceSiliconGPR120PREFERENCEchemistry.chemical_elementPhysics::Optics02 engineering and technologyDielectric01 natural sciencesRATS010309 opticsALPHA-GUSTDUCIN0103 physical sciencesSensitivity (control systems)DIETARY LIPIDSElectrical and Electronic EngineeringPlasmonRECEPTORbusiness.industry021001 nanoscience & nanotechnologyACIDSAtomic and Molecular Physics and OpticsElectronic Optical and Magnetic MaterialsMICEchemistryPlasmonic waveguideTransmission (telecommunications)Silicon chipOptoelectronicsSENSITIVITY0210 nano-technologybusinessData transmission
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Automatic optimization of multichip RFID tags

2012

The automatic optimization is proposed of the passive RF part of RFID, with special attention to multi-chip tags, and to the novel concept of RFID grids. Performance metrics follows a recent all-comprehensive approach. The proposed approach employs a Genetic Algorithm-based optimization, and an efficient electromagnetic problem parameterization and solution strategy. Resulting structures, while non-intuitive in shape, exhibit enhanced performance.

Electromagnetic fieldRFIDmethod of momentsComputer scienceGenetic Algorithmsmultichip tagtag antennaRFID multi-port antennaRFID; multichip tag; Genetic AlgorithmsmultichipGenetic algorithmElectronic engineeringgenetic algorithmoptimization
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Mobile Phone Chips Reduce Increases in EEG Brain Activity Induced by Mobile Phone-Emitted Electromagnetic Fields

2018

Recent neurophysiological studies indicate that exposure to electromagnetic fields (EMFs) generated by mobile phone radiation can exert effects on brain activity. One technical solution to reduce effects of EMFs in mobile phone use is provided in mobile phone chips that are applied to mobile phones or attached to their surfaces. To date, there are no systematical studies on the effects of mobile phone chip application on brain activity and the underlying neural mechanisms. The present study investigated whether mobile phone chips that are applied to mobile phones reduce effects of EMFs emitted by mobile phone radiation on electroencephalographic (EEG) brain activity in a laboratory study. T…

Electromagnetic fieldmedicine.medical_specialtyComputer scienceBrain activity and meditationElectroencephalographyAudiologyelectromagnetic fields exposure050105 experimental psychologyRadio spectrumlcsh:RC321-571mobile phone radiation03 medical and health sciences0302 clinical medicineMobile phone radiation and healthmedicine0501 psychology and cognitive sciencesCorrelational analysislcsh:Neurosciences. Biological psychiatry. NeuropsychiatryOriginal Researchmedicine.diagnostic_testGeneral Neuroscience05 social sciencesChipattentionmobile phone chipsMobile phoneelectroencephalography030217 neurology & neurosurgeryNeuroscienceFrontiers in Neuroscience
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A computational approach to evaluate temperature and heat partition in machining with multilayer coated tools

2003

Abstract In this paper, analytical models for estimating the interface temperature and heat partition to the chip in continuous dry machining of steels with flat-faced tools treated with multilayer coatings are presented. The database for modeling includes changes in the thermal properties of both workpiece and substrate/coating materials and the Peclet and Fourier numbers occurring at actual interface temperatures. Process outputs involve the average tool–chip interface temperature, the tool–chip contact length, the friction energy and the heat balance between the moving chip and stationary tool. It was found that the heat partition coefficient varies significantly from 0.65 to 0.8 when us…

Engineering drawingMaterials scienceMechanical EngineeringChipIndustrial and Manufacturing EngineeringCarbidePartition coefficientSubstrate (building)symbols.namesakeFourier transformMachiningThermalsymbolsPartition (number theory)Composite materialInternational Journal of Machine Tools and Manufacture
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On the impact of within-die process variation in GALS-Based NoC Performance

2012

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at design time. In this paper, we first analyze the way that manufacturing deviations affect the components of a NoC by applying a new comprehensive and detailed within-die variability model to 200 instances of an 8¿8 mesh NoC synthesized using 45 nm technology. Later, we show that GALS-based NoCs pr…

Engineering02 engineering and technology01 natural sciencesExecution timeDie (integrated circuit)Networks-on-chipReduction (complexity)0103 physical sciencesSynchronization (computer science)0202 electrical engineering electronic engineering information engineeringGALSElectrical and Electronic Engineering010302 applied physicsbusiness.industryChipComputer Graphics and Computer-Aided Design020202 computer hardware & architectureProcess variationARQUITECTURA Y TECNOLOGIA DE COMPUTADORESProcess variationNetwork on a chipLogic gateEmbedded systembusinessSoftware
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ALE Simulation of Orthogonal Cutting: a New Approach to Model Heat Transfer Phenomena at the Tool-Chip Interface

2007

This paper presents a new procedure to evaluate the global heat transfer coefficient in orthogonal cutting. The knowledge of the actual heat transfer conditions is a fundamental issue as far as the life, tool wear and tool substitution interval are regarded. More in detail, an Arbitrary Lagrangian-Eulerian approach was utilised to model orthogonal cutting process and the numerical simulations were validated by making experimental tests for identifying cutting forces and internal tool temperatures. A mild steel was cut utilising both an uncoated (WC) and a coated (TiN) tool. On the basis of both experimental and simulative data, a consistent model of the global heat transfer coefficient as f…

EngineeringBasis (linear algebra)business.industryMechanical EngineeringInterface (computing)finite element methodProcess (computing)Mechanical engineeringInterval (mathematics)Heat transfer coefficientChipIndustrial and Manufacturing Engineeringheat transfer coefficientHeat transferTool wearbusinesscuttingSettore ING-IND/16 - Tecnologie E Sistemi Di LavorazioneCIRP Annals
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Smart cameras on a chip: using complementary metal-oxide-semiconductor (CMOS) image sensors to create smart vision chips

2020

Abstract: In this chapter, we introduce the fundamental concept of smart cameras on a chip or smart vision chips that simultaneously integrate the same die image capture capability and highly complex image processing. Successive technology scaling has made possible the integration of specific processing elements designed at chip level, at column level or at pixel level. To illustrate this continuous evolution, we survey three different categories of vision chips, exploring first the pioneering works on artificial retinas, then describing the most significant computational chips, and finally presenting the most recent image processing chips able to perform complex algorithms at a high frame …

EngineeringCMOSPixelbusiness.industryComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISIONElectronic engineeringImage processingSmart cameraImage sensorFrame ratebusinessChipDie (integrated circuit)
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Monolithic integration of GMR sensors for standard CMOS-IC current sensing

2017

Abstract In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a de…

EngineeringCmos asicHardware_PERFORMANCEANDRELIABILITY02 engineering and technologyIntegrated circuit01 natural scienceslaw.inventionApplication-specific integrated circuitlawHardware_INTEGRATEDCIRCUITSMaterials ChemistrySystem on a chipElectrical and Electronic Engineeringbusiness.industry010401 analytical chemistryElectrical engineering021001 nanoscience & nanotechnologyCondensed Matter Physics0104 chemical sciencesElectronic Optical and Magnetic MaterialsCMOSInterfacingCurrent (fluid)0210 nano-technologybusinessSensitivity (electronics)Solid-State Electronics
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An Investigation of the Cutting Process for Chip Breaking Monitoring in Turning of Steels

1998

This paper presents some results of an experimental study on chip breaking monitoring when turning steels with chip forming inserts. In the first part of this study the recognition of chip forms by means of cutting force analysis in the frequency domain is described. Generally, the present work is concerned with the use of the interface control factor for determining the transition from unacceptable chip forms to the chip breaking. For this purpose experiments under approximately orthogonal machining conditions including measuring the shear strain, the cutting energy and the average interface temperature are carried out. The obtained results confirmed that the initiation of acceptable chip …

EngineeringFrequency responseEngineering drawingSignal processingbusiness.industryMechanical EngineeringProcess (computing)Mechanical engineeringEnergy consumptionChipIndustrial and Manufacturing EngineeringComputer Science ApplicationsMachiningControl and Systems EngineeringFrequency domainbusinessEnergy (signal processing)Journal of Manufacturing Science and Engineering
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Hierarchical control with virtual resistance optimization for efficiency enhancement and State-of-Charge balancing in DC microgrids

2015

This paper proposes a hierarchical control scheme which applies optimization method into DC microgrids in order to improve the system overall efficiency while considering the State-of-Charge (SoC) balancing at the same time. Primary droop controller, secondary voltage restoration controller and tertiary optimization tool formulate the complete hierarchical control system. Virtual resistances are taken as the decision variables for achieving the objective. simulation results are presented to verify the proposed approach.

EngineeringHierarchical controlLinear programmingbusiness.industryControl engineeringEfficiencyState-of-chargeSettore ING-IND/33 - Sistemi Elettrici Per L'Energiaefficiency genetic algorithm hierarchical control state-of-chargeState of chargeGenetic algorithmControl theoryGenetic algorithmHierarchical control systemSystem on a chipVoltage droopAlgorithm designbusiness2015 IEEE First International Conference on DC Microgrids (ICDCM)
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